US5808958A
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Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock
Assignee: Texas Instruments Inc
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Filing: 1995-06-07
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Granted: 1998-09-15
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Expires: 2015-06-07
Abstract
Abstract A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
Inventors
- 👤 Wilbur Christian Vogley
- 👤 Anthony Michael Balistreri
- 👤 Karl M. Guttag
- 👤 Steven D. Krueger
- 👤 Duy-Loan T. Le
- 👤 Joseph H. Neal
- 👤 Kenneth A. Poteet
- 👤 Joseph P. Hartigan
- 👤 Roger D. Norwood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:30
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C7/1015; G11C7/1018; G11C7/1072
Claims Analysis
Total Claims: 78
Claim 1
Independent Claim
200 words
A data processing system comprising: a digital processor; a system clock circuit for producing a system clock signal for controlling operation of the digital processor; a synchronous random access memory, responsive to the system clock signal, for accessing addressable storage cells within the synchronous memory to write data into the storage cells and to read out data from the storage cells; and the synchronous random access memory receiving a first address signal for accessing the storage cells within the synchronous random access memory, responsive to the system clock signal, the synchronous random access memory comprising: a timing and control circuit for producing a first address control signal and a first data control signal; an addressing circuit for latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a predetermined number of data bits from the storage cells, responsive to the system clock signal, wherein the first data control signal selects the predetermined number of data bits and the output circuit produces a first datum bit of the predetermined number of data bits, responsive to another clock cycle of the system clock signal.
Claim 2
Dependent Claim
200 words
A data processing system comprising: a digital processor; a system clock circuit for producing a system clock signal for controlling operation of the digital processor; a synchronous random access memory, responsive to the system clock signal, for accessing addressable storage cells within the synchronous memory to write data into the storage cells and to read out data from the storage cells; and the synchronous random access memory receiving a first address signal for accessing the storage cells within the synchronous random access memory, responsive to the system clock signal, the synchronous random access memory comprising: a timing and control circuit for producing a first address control signal and a first data control signal; an addressing circuit for latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a predetermined number of data bits from the storage cells, responsive to the system clock signal, wherein the first data control signal selects the predetermined number of data bits and the output circuit produces a first datum bit of the predetermined number of data bits, responsive to another clock cycle of the system clock signal.
Claim 3
Dependent Claim
105 words
A data processing system, in accordance with claim 1, wherein the addressing circuit further comprises: row address circuitry, responsive to the first address signal, for accessing a row of the addressable storage cells to write data in or to read data out of the synchronous memory; an address counter circuit for receiving a second address signal, the address counter circuit producing an output address signal, responsive to the system clock signal; and column address circuitry, responsive to the output address signal, for accessing a block of columns of the addressable storage cells to write data in or to read data out of the synchronous memory.
Claim 4
Dependent Claim
44 words
A data processing system, in accordance with claim 2, wherein the addressing circuit latches the second address signal, responsive to a second address control signal and a second clock cycle of the system clock signal, the second clock cycle following the first clock cycle.
Claim 5
Dependent Claim
31 words
A data processing system, in accordance with claim 3, wherein the address counter circuit produces the output address signal by incrementing the second address signal, responsive to the system clock signal.
Claim 6
Dependent Claim
34 words
A data processing system, in accordance with claim 3, wherein the timing and control circuit further determines an order of the predetermined number of data bits in response to a second data control signal.
Claim 7
Dependent Claim
24 words
A data processing system, in accordance with claim 5, wherein the order of the predetermined number of data bits is by sequential column address.
Claim 8
Dependent Claim
24 words
A data processing system, in accordance with claim 5, wherein the order of the predetermined number of data bits is by interleaved wrap sequence.
Claim 9
Dependent Claim
39 words
A data processing system, in accordance with claim 5, wherein the first address control signal is produced in response to a row enable signal, and the second address control signal is produced in response to a column enable signal.
Claim 10
Dependent Claim
23 words
A data processing system, in accordance with claim 5, wherein the another clock cycle is two clock cycles after the second clock cycle.
Claim 11
Dependent Claim
17 words
A data processing system, in accordance with claim 1, wherein the storage cells are dynamic storage cells.
Claim 12
Dependent Claim
18 words
A data processing system, in accordance with claim 10, wherein the predetermined number of data bits is 4.
Claim 13
Dependent Claim
147 words
A synchronous random access memory comprising: an array of storage cells arranged in addressable rows and columns; a timing and control circuit for receiving a system clock signal and producing a first address control signal and a first data control signal; an addressing circuit for receiving a first address signal for accessing the storage cells within the synchronous random access memory, the addressing circuit latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a predetermined number of data bits from the storage cells, responsive to the system clock signal, wherein the first data control signal selects the predetermined number of data bits and the output circuit produces a first datum bit of the predetermined number of data bits, responsive to another clock cycle of the system clock signal.
Claim 14
Dependent Claim
147 words
A synchronous random access memory comprising: an array of storage cells arranged in addressable rows and columns; a timing and control circuit for receiving a system clock signal and producing a first address control signal and a first data control signal; an addressing circuit for receiving a first address signal for accessing the storage cells within the synchronous random access memory, the addressing circuit latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a predetermined number of data bits from the storage cells, responsive to the system clock signal, wherein the first data control signal selects the predetermined number of data bits and the output circuit produces a first datum bit of the predetermined number of data bits, responsive to another clock cycle of the system clock signal.
Claim 15
Dependent Claim
18 words
A synchronous random access memory, in accordance with claim 12, wherein the storage cells are dynamic storage cells.
Claim 16
Dependent Claim
18 words
A synchronous random access memory as in claim 13, wherein the predetermined number of data bits is 4.
Claim 17
Dependent Claim
19 words
A synchronous random access memory, in accordance with claim 13, wherein the predetermined number of data bits is 8.
Claim 18
Dependent Claim
85 words
A synchronous random access memory, in accordance with claim 13, wherein the addressing circuit further comprises: a row decoding circuit for selecting a row of the storage cells, responsive to the first address signal; an address counter circuit for receiving a second address signal, the address counter circuit producing an output address signal, responsive to the system clock signal; and a column decoding circuit for selecting a column of the storage cells from the row of the storage cells, responsive to the output address signal.
Claim 19
Dependent Claim
45 words
A synchronous random access memory in accordance with claim 16, wherein the addressing circuit latches the second address signal, responsive to a second address control signal and a second clock cycle of the system clock signal, the second clock cycle following the first clock cycle.
Claim 20
Dependent Claim
32 words
A synchronous random access memory in accordance with claim 17, wherein the address counter circuit produces the output address signal by incrementing the second address signal, responsive to the system clock signal.
Claim 21
Dependent Claim
35 words
A synchronous random access memory, in accordance with claim 17, wherein the timing and control circuit further determines an order of the predetermined number of data bits in response to a second data control signal.
Claim 22
Dependent Claim
25 words
A synchronous random access memory, in accordance with claim 19, wherein the order of the predetermined number of data bits is by sequential column address.
Claim 23
Dependent Claim
25 words
A synchronous random access memory, in accordance with claim 19, wherein the order of the predetermined number of data bits is by interleaved wrap sequence.
Claim 24
Dependent Claim
40 words
A synchronous random access memory, in accordance with claim 19, wherein the first address control signal is produced in response to a row enable signal, and the second address control signal is produced in response to a column enable signal.
Claim 25
Dependent Claim
24 words
A synchronous random access memory, in accordance with claim 19, wherein the another clock cycle is two clock cycles after the second clock cycle.
Claim 26
Dependent Claim
25 words
A synchronous random access memory, in accordance with claim 12, wherein the first address signal includes a first and a second group of address bits.
Claim 27
Dependent Claim
89 words
A synchronous random access memory, in accordance with claim 24, wherein the addressing circuit further comprises: a row decoding circuit for selecting a row of the storage cells, responsive to the first group of address bits; an address counter circuit for receiving the second group of address bits, the address counter circuit producing an output address signal, responsive to the system clock signal; and a column decoding circuit for selecting a column of the storage cells from the row of the storage cells, responsive to the output address signal.
Claim 28
Dependent Claim
28 words
A synchronous random access memory, in accordance with claim 25, wherein the address counter circuit produces the output address signal by incrementing the second group of address bits.
Claim 29
Dependent Claim
19 words
A synchronous random access memory, in accordance with claim 25, wherein the predetermined number of data bits is 4.
Claim 30
Dependent Claim
19 words
A synchronous random access memory, in accordance with claim 25, wherein the predetermined number of data bits is 8.
Claim 31
Dependent Claim
35 words
A synchronous random access memory, in accordance with claim 25, wherein the timing and control circuit further determines an order of the predetermined number of data bits in response to a second data control signal.
Claim 32
Dependent Claim
25 words
A synchronous random access memory, in accordance with claim 29, wherein the order of the predetermined number of data bits is by sequential column address.
Claim 33
Dependent Claim
25 words
A synchronous random access memory, in accordance with claim 29, wherein the order of the predetermined number of data bits is by interleaved wrap sequence.
Claim 34
Dependent Claim
24 words
A synchronous random access memory, in accordance with claim 29, wherein the another clock cycle is two clock cycles after the first clock cycle.
Claim 35
Dependent Claim
18 words
A synchronous random access memory, in accordance with claim 29, wherein the storage cells are static storage cells.
Claim 36
Dependent Claim
223 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal for controlling operation of the digital processor, the system clock signal having a sequence of periodic clock cycles; and a synchronous dynamic random access memory, responsive to the system clock signal, receiving a first and a second address signal for accessing addressable storage cells within the synchronous dynamic random access memory, the synchronous dynamic random access memory comprising: a timing and control circuit for producing a first address control signal and a first data control signal; a row decoding circuit for selecting a row of the storage cells, responsive to the first address signal; an address counter circuit for receiving the second address signal, the address counter circuit producing an output address signal, responsive to the system clock signal; and a column decoding circuit for selecting a column of the storage cells from the row of the storage cells, responsive to the output address signal; and an output circuit for producing a plurality of data bits from the storage cells, responsive to the system clock signal, the plurality of data bits having an order determined by the first data control signal, the output circuit producing a first datum bit of the plurality of data bits, responsive to another clock cycle of the system clock signal.
Claim 37
Dependent Claim
223 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal for controlling operation of the digital processor, the system clock signal having a sequence of periodic clock cycles; and a synchronous dynamic random access memory, responsive to the system clock signal, receiving a first and a second address signal for accessing addressable storage cells within the synchronous dynamic random access memory, the synchronous dynamic random access memory comprising: a timing and control circuit for producing a first address control signal and a first data control signal; a row decoding circuit for selecting a row of the storage cells, responsive to the first address signal; an address counter circuit for receiving the second address signal, the address counter circuit producing an output address signal, responsive to the system clock signal; and a column decoding circuit for selecting a column of the storage cells from the row of the storage cells, responsive to the output address signal; and an output circuit for producing a plurality of data bits from the storage cells, responsive to the system clock signal, the plurality of data bits having an order determined by the first data control signal, the output circuit producing a first datum bit of the plurality of data bits, responsive to another clock cycle of the system clock signal.
Claim 38
Dependent Claim
45 words
A data processing system, in accordance with claim 34, wherein the address counter circuit latches the second address signal, responsive to a second address control signal and a second clock cycle of the system clock signal, the second clock cycle following a first clock cycle.
Claim 39
Dependent Claim
41 words
A data processing system as in claim 35, wherein the output circuit produces a predetermined number of data bits from the storage cells, responsive to a second data control signal from the timing and control circuit and the system clock signal.
Claim 40
Dependent Claim
141 words
A synchronous random access memory comprising: an array of addressable storage cells; a timing and control circuit for receiving a system clock signal and producing a first address control signal and a first data control signal; an addressing circuit for receiving a first address signal for accessing the storage cells within the synchronous random access memory, the addressing circuit latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a plurality of data bits from the storage cells, responsive to the system clock signal, the plurality of data bits having an order determined by the first data control signal, the output circuit producing a first datum bit of the plurality of data bits, responsive to another clock cycle of the system clock signal.
Claim 41
Dependent Claim
141 words
A synchronous random access memory comprising: an array of addressable storage cells; a timing and control circuit for receiving a system clock signal and producing a first address control signal and a first data control signal; an addressing circuit for receiving a first address signal for accessing the storage cells within the synchronous random access memory, the addressing circuit latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a plurality of data bits from the storage cells, responsive to the system clock signal, the plurality of data bits having an order determined by the first data control signal, the output circuit producing a first datum bit of the plurality of data bits, responsive to another clock cycle of the system clock signal.
Claim 42
Dependent Claim
18 words
A synchronous random access memory, in accordance with claim 37, wherein the storage cells are dynamic storage cells.
Claim 43
Dependent Claim
23 words
A synchronous random access memory as in claim 38, wherein the order of the plurality of data bits is by sequential column address.
Claim 44
Dependent Claim
24 words
A synchronous random access memory, in accordance with claim 38, wherein the order of the plurality of data bits is by interleaved wrap sequence.
Claim 45
Dependent Claim
83 words
A synchronous random access memory as in claim 38, wherein the addressing circuit further comprises: a row decoding circuit for selecting a row of the storage cells, responsive to the first address signal; an address counter circuit for receiving a second address signal, the address counter circuit producing an output address signal, responsive to the system clock signal; and a column decoding circuit for selecting a column of the storage cells from the row of storage cells, responsive to the output address signal.
Claim 46
Dependent Claim
44 words
A synchronous random access memory as in claim 41, wherein the addressing circuit latches the second address signal, responsive to a second address control signal and a second clock cycle of the system clock signal, the second clock cycle following the first clock cycle.
Claim 47
Dependent Claim
31 words
A synchronous random access memory as in claim 42, wherein the address counter circuit produces the output address signal by incrementing the second address signal, responsive to the system clock signal.
Claim 48
Dependent Claim
49 words
A synchronous random access memory as in claim 42, wherein the first address control signal is produced in response to a row enable signal and the system clock signal, and the second address control signal is produced in response to a column enable signal and the system clock signal.
Claim 49
Dependent Claim
23 words
A synchronous random access memory as in claim 42, wherein the another clock cycle is two clock cycles after the second clock cycle.
Claim 50
Dependent Claim
24 words
A synchronous random access memory as in claim 37, wherein the first address signal includes a first and a second group of address bits.
Claim 51
Dependent Claim
88 words
A synchronous random access memory as in claim 46, wherein the addressing circuit further comprises: a row decoding circuit for selecting a row of the storage cells, responsive to the first group of address bits; an address counter circuit for receiving the second group of address bits, the address counter circuit producing an output address signal, responsive to the system clock signal; and a column decoding circuit for selecting a column of the storage cells from the row of the storage cells, responsive to the output address signal.
Claim 52
Dependent Claim
27 words
A synchronous random access memory as in claim 47, wherein the address counter circuit produces the output address signal by incrementing the second group of address bits.
Claim 53
Dependent Claim
23 words
A synchronous random access memory as in claim 47, wherein the order of the plurality of data bits is by sequential column address.
Claim 54
Dependent Claim
23 words
A synchronous random access memory as in claim 47, wherein the order of the plurality of data bits is by interleaved wrap sequence.
Claim 55
Dependent Claim
23 words
A synchronous random access memory as in claim 47, wherein the another clock cycle is two clock cycles after the first clock cycle.
Claim 56
Dependent Claim
17 words
A synchronous random access memory as in claim 47, wherein the storage cells are static storage cells.
Claim 57
Dependent Claim
196 words
A data processing system comprising: a digital processor; an input peripheral device interconnected with the digital processor; an output peripheral device interconnected with the digital processor; a system clock circuit, producing a system clock signal, for controlling operation of the digital processor, the input peripheral device, and the output peripheral device; and a synchronous dynamic random access memory including an array of addressable storage cells; a timing and control circuit for receiving the system clock signal and producing a first address control signal and a first data control signal; an addressing circuit for receiving a first address signal for accessing the storage cells within the synchronous dynamic random access memory, the addressing circuit latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a predetermined number of data bits from the storage cells, responsive to the system clock signal, wherein the first data control signal selects the predetermined number of data bits and the output circuit produces a first datum bit of the predetermined number of data bits, responsive to another clock cycle of the system clock signal.
Claim 58
Dependent Claim
196 words
A data processing system comprising: a digital processor; an input peripheral device interconnected with the digital processor; an output peripheral device interconnected with the digital processor; a system clock circuit, producing a system clock signal, for controlling operation of the digital processor, the input peripheral device, and the output peripheral device; and a synchronous dynamic random access memory including an array of addressable storage cells; a timing and control circuit for receiving the system clock signal and producing a first address control signal and a first data control signal; an addressing circuit for receiving a first address signal for accessing the storage cells within the synchronous dynamic random access memory, the addressing circuit latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a predetermined number of data bits from the storage cells, responsive to the system clock signal, wherein the first data control signal selects the predetermined number of data bits and the output circuit produces a first datum bit of the predetermined number of data bits, responsive to another clock cycle of the system clock signal.
Claim 59
Dependent Claim
25 words
A data processing system as in claim 53, wherein the predetermined number of data bits have an order determined by a second data control signal.
Claim 60
Dependent Claim
24 words
A data processing system as in claim 54, wherein the input peripheral device is coupled to the digital processor by a first data bus.
Claim 61
Dependent Claim
26 words
A data processing system as in claim 55, wherein the synchronous dynamic random access memory is coupled to the digital processor by a second data bus.
Claim 62
Dependent Claim
24 words
A data processing system as in claim 56, wherein the output peripheral device is coupled to the digital processor by a third data bus.
Claim 63
Dependent Claim
208 words
A data processing system comprising: a digital processor; an input peripheral device interconnected with the digital processor; an output peripheral device interconnected with the digital processor; a system clock circuit, producing a system clock signal for controlling operation of the digital processor, the digital processor producing a gated clock signal for controlling operation of the input peripheral device and the output peripheral device; and a synchronous dynamic random access memory including an array of addressable storage cells; a timing and control circuit for receiving the system clock signal and producing a first address control signal and a first data control signal; an addressing circuit for receiving a first address signal for accessing the storage cells within the synchronous dynamic random access memory, the addressing circuit latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a predetermined number of data bits from the storage cells, responsive to the system clock signal, wherein the first data control signal selects the predetermined number of data bits and the output circuit produces a first datum bit of the predetermined number of data bits, responsive to another clock cycle of the system clock signal.
Claim 64
Dependent Claim
208 words
A data processing system comprising: a digital processor; an input peripheral device interconnected with the digital processor; an output peripheral device interconnected with the digital processor; a system clock circuit, producing a system clock signal for controlling operation of the digital processor, the digital processor producing a gated clock signal for controlling operation of the input peripheral device and the output peripheral device; and a synchronous dynamic random access memory including an array of addressable storage cells; a timing and control circuit for receiving the system clock signal and producing a first address control signal and a first data control signal; an addressing circuit for receiving a first address signal for accessing the storage cells within the synchronous dynamic random access memory, the addressing circuit latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a predetermined number of data bits from the storage cells, responsive to the system clock signal, wherein the first data control signal selects the predetermined number of data bits and the output circuit produces a first datum bit of the predetermined number of data bits, responsive to another clock cycle of the system clock signal.
Claim 65
Dependent Claim
25 words
A data processing system as in claim 58, wherein the predetermined number of data bits have an order determined by a second data control signal.
Claim 66
Dependent Claim
24 words
A data processing system as in claim 59, wherein the input peripheral device is coupled to the digital processor by a first data bus.
Claim 67
Dependent Claim
26 words
A data processing system as in claim 60, wherein the synchronous dynamic random access memory is coupled to the digital processor by a second data bus.
Claim 68
Dependent Claim
24 words
A data processing system as in claim 61, wherein the output peripheral device is coupled to the digital processor by a third data bus.
Claim 69
Dependent Claim
174 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal for controlling operation of the digital processor, the system clock signal having a sequence of periodic clock cycles; and a synchronous random access memory, responsive to the system clock signal, receiving a first address signal for accessing addressable storage cells within the synchronous random access memory, the synchronous random access memory comprising: a timing and control circuit for producing a first address control signal and a first data control signal; an addressing circuit for latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a plurality of data bits from the storage cells, responsive to the system clock signal, the plurality of data bits having an order determined by the first data control signal, the output circuit producing a first datum bit of the plurality of data bits, responsive to another clock cycle of the system clock signal.
Claim 70
Dependent Claim
174 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal for controlling operation of the digital processor, the system clock signal having a sequence of periodic clock cycles; and a synchronous random access memory, responsive to the system clock signal, receiving a first address signal for accessing addressable storage cells within the synchronous random access memory, the synchronous random access memory comprising: a timing and control circuit for producing a first address control signal and a first data control signal; an addressing circuit for latching the first address signal, responsive to the first address control signal and a first clock cycle of the system clock signal; and an output circuit for producing a plurality of data bits from the storage cells, responsive to the system clock signal, the plurality of data bits having an order determined by the first data control signal, the output circuit producing a first datum bit of the plurality of data bits, responsive to another clock cycle of the system clock signal.
Claim 71
Dependent Claim
24 words
A data processing system, in accordance with claim 63, wherein the first address signal includes a first and a second group of address bits.
Claim 72
Dependent Claim
86 words
A data processing system as in claim 64, wherein the addressing circuit further comprises: a row decoding circuit for selecting a row of the storage cells, responsive to the first group of address bits; an address counter circuit for receiving the second group of address bits, the address counter circuit producing an output address signal, responsive to the system clock signal; and a column decoding circuit for selecting a column of the storage cells from the row of storage cells, responsive to the output address signal.
Claim 73
Dependent Claim
26 words
A data processing system as in claim 65, wherein the address counter circuit produces the output address signal by incrementing the second group of address bits.
Claim 74
Dependent Claim
22 words
A data processing system as in claim 63, wherein the order of the plurality of data bits is by sequential column address.
Claim 75
Dependent Claim
22 words
A data processing system as in claim 63, wherein the order of the plurality of data bits is by interleaved wrap sequence.
Claim 76
Dependent Claim
22 words
A data processing system as in claim 63, wherein the another clock cycle is two clock cycles after the first clock cycle.
Claim 77
Dependent Claim
16 words
A data processing system as in claim 63, wherein the storage cells are static storage cells.
Claim 78
Dependent Claim
41 words
A data processing system as in claim 63, wherein the output circuit produces a predetermined number of data bits from the storage cells, responsive to a second data control signal from the timing and control circuit and the system clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |