US4394753A
Expired / Lapsed
US
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Integrated memory module having selectable operating functions
Assignee: Siemens AG
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Filing: 1980-11-12
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Granted: 1983-07-19
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Expires: 2000-11-12
Abstract
Abstract An integrated memory module has operating functions which are selectable even after the module has been built-in. A significant expansion of the possibilities of use of the memory module is achieved by the introduction of an inscribable and readable mode register for the acceptance of control information for defining the desired operating function, by the expansion of the address inputs into bidirectional module interfaces, and by the subdivision of the memory medium which is constructed as a matrix into n areas of identical size which are simultaneously addressable with the most significant portion of the column address. An internal address counter also permits accesses with consecutive column addresses given constant row address.
Inventors
- 👤 Hans-Joerg Penzel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085; G11C5/00; G11C5/06; G11C5/066; G11C7/00; G11C7/10; G11C7/1006; G11C7/1015; G11C7/103; G11C7/1033; G11C7/1045; G11C7/22; G11C8/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
267 words
In an integrated memory module of the type in which a plurality of memory cells are arranged in a matrix of columns and rows and are addressable by row and column addresses received via a plurality of address terminals in response to strobe signals to provide data on a plurality of write/read lines, in which a bidirectional address buffer is connected to the address terminals for receiving an address, and in which a row address decoder and a column address decoder are connected between the address buffer and the rows and columns of memory cells, respectively, for producing row and column selection signals, the improvement therein comprising: a data bus connected to said memory and having a plurality of lines equal to the number n of write/read lines to be selected by a higher value portion of a column address; a mode register operable to receive and store mode signals from and to provide mode signals for the address terminals, the mode signals defining the operating functions of the memory module, in response to predetermined control signals; a bidirectional data input and data output device connected to said data bus; said memory matrix divided into small n areas each including an identical plurality of columns of memory cells and all said areas being simultaneously accessible; and a switch circuit, including a bidirectional operating portion, and selectively operable to connect the address buffer to the address decoders, to connect the address buffer to the mode register and to connect the address register to the data bus in response to receipt of other control signals including the strobe signals.
Claim 2
Dependent Claim
267 words
In an integrated memory module of the type in which a plurality of memory cells are arranged in a matrix of columns and rows and are addressable by row and column addresses received via a plurality of address terminals in response to strobe signals to provide data on a plurality of write/read lines, in which a bidirectional address buffer is connected to the address terminals for receiving an address, and in which a row address decoder and a column address decoder are connected between the address buffer and the rows and columns of memory cells, respectively, for producing row and column selection signals, the improvement therein comprising: a data bus connected to said memory and having a plurality of lines equal to the number n of write/read lines to be selected by a higher value portion of a column address; a mode register operable to receive and store mode signals from and to provide mode signals for the address terminals, the mode signals defining the operating functions of the memory module, in response to predetermined control signals; a bidirectional data input and data output device connected to said data bus; said memory matrix divided into small n areas each including an identical plurality of columns of memory cells and all said areas being simultaneously accessible; and a switch circuit, including a bidirectional operating portion, and selectively operable to connect the address buffer to the address decoders, to connect the address buffer to the mode register and to connect the address register to the data bus in response to receipt of other control signals including the strobe signals.
Claim 3
Dependent Claim
128 words
The improved memory module of claim 1, and further comprising: an address memory connected to said switch circuit for receiving the lower value bits of a column address and column address strobe signals and operable to change the counter output signals step-by-step for a predetermined number of and in response to receipt of column address strobe signals; and said data input and data output device including a multiplexer connected to said address counter and to said data bus, said multiplexer including a data input and a data output and operable in response to the counter output signals to selectively connect either said data input or said data output to one of n memory cells selected by a row address and the higher value bits of a column address.
Claim 4
Dependent Claim
127 words
The improved memory module of claim 2, and further comprising: a further multiplexer interposed between the memory matrix and said data bus; and a further address counter connected between said switch circuit and said further multiplexer for receiving a plurality of mean significant bits of a column address and operable to count, alternatively to the counting by the first-mentioned address counter, step-by-step in response to receipt of column strobe signals to modify the received portion of the column address, said matrix being further divided into k subareas of equal size which are simultaneously addressable by the highest value bits of a column adddress, said further multiplexer operable to connect said data bus and respectively k write/read lines of one of the n areas of the memory matrix.
References Cited (Backward Citations)
US3755791A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-18 | 1987-01-17 | 1987-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-18 | 1991-01-17 | 1991-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-18 | 1995-01-17 | 1995-07-19 | $7700.00 | Window Closed / Lapsed |