US5400288A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory chip
Assignee: Texas Instruments Inc
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Filing: 1993-12-29
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Granted: 1995-03-21
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Expires: 2013-12-29
Abstract
Abstract A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
Inventors
- 👤 Masashi Hashimoto
- 👤 Gene A. Frantz
- 👤 John V. Moravec
- 👤 Jean-Pierre Dolait
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:15
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/391; H; H04; H04B; H04B7/00; H04B7/14; H04B7/15; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/103; G11C7/1036; G11C7/1072; G11C7/1075; H04B7/185; H04B7/18502
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
122 words
A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising: a write address input port including a single lead for serially receiving bits of a start write address for a sequence of memory access operations; a write address sequencer, connected to the write address input port and responsive to the start write address and a first clock signal, for generating a sequence of memory write addresses, commencing with the start write address, which are applied to the decoder; and a data input port for receiving a sequence of data signals and for loading the received data signals sequentially into the memory addresses generated by the write address sequencer.
Claim 2
Dependent Claim
122 words
A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising: a write address input port including a single lead for serially receiving bits of a start write address for a sequence of memory access operations; a write address sequencer, connected to the write address input port and responsive to the start write address and a first clock signal, for generating a sequence of memory write addresses, commencing with the start write address, which are applied to the decoder; and a data input port for receiving a sequence of data signals and for loading the received data signals sequentially into the memory addresses generated by the write address sequencer.
Claim 3
Dependent Claim
115 words
A semiconductor memory chip, in accordance with claim 1, further comprising: a read address input port including a single lead for serially receiving bits of a start read address for a sequence of memory access operations; a read address sequencer, connected to the read address input port and responsive to the start read address and a second clock signal, for generating a sequence of memory read addresses, commencing with the start read address, which are applied to the decoder; and a data output port arranged for receiving a sequence of data signals read from the memory addresses generated by the read address sequencer and for transmitting the sequence of data signals read from the memory.
Claim 4
Dependent Claim
139 words
A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising: a write address input port including a single lead for serially receiving a start write address for a sequence of memory access operations; a write address sequencer, connected to the write address input port and responsive to the start write address and a first clock signal, for generating a sequence of memory write addresses commencing with the start write address, which are applied to the decoder, sequential ones of the memory write addresses being incremented from the prior memory write address by an offset value; and a data input port for receiving a sequence of data signals and for loading the received data signals sequentially into the memory addresses generated by the write address sequencer.
Claim 5
Dependent Claim
139 words
A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising: a write address input port including a single lead for serially receiving a start write address for a sequence of memory access operations; a write address sequencer, connected to the write address input port and responsive to the start write address and a first clock signal, for generating a sequence of memory write addresses commencing with the start write address, which are applied to the decoder, sequential ones of the memory write addresses being incremented from the prior memory write address by an offset value; and a data input port for receiving a sequence of data signals and for loading the received data signals sequentially into the memory addresses generated by the write address sequencer.
Claim 6
Dependent Claim
32 words
A semiconductor memory chip, in accordance with claim 3, wherein the write address sequencer is arranged to increment sequential ones of the memory write addresses by an offset value equal to one.
Claim 7
Dependent Claim
32 words
A semiconductor memory chip, in accordance with claim 3, wherein the write address sequencer is arranged to increment sequential ones of the memory write addresses by an offset value greater than one.
Claim 8
Dependent Claim
27 words
A semiconductor memory chip, in accordance with claim 3, wherein the write address sequencer is arranged to increment the memory write addresses by a variable offset value.
Claim 9
Dependent Claim
261 words
A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising: a write address input port including a single lead for serially receiving a start write address for a sequence of memory access operations; a write address sequencer, connected to the write address input port and responsive to the start write address and a first clock signal, for generating a sequence of memory write addresses, commencing with the start write address, which are applied to the decoder, the write address sequencer being arranged to increment sequential ones of the memory write addresses by a variable offset value; a data input port for receiving a sequence of data signals and for loading the received data signals sequentially into the memory addresses generated by the write address sequencer; a read address input port including a single lead for serially receiving a start read address for a sequence of memory access operations; a read address sequencer, connected to the read address input port and responsive to the start read address and a second clock signal, for generating a sequence of memory read addresses, commencing with the start read address, which are applied to the decoder, the read address sequencer being arranged to increment sequential ones of the memory read addresses by a variable offset value; and a data output port arranged for receiving a sequence of data signals read from the memory addresses generated by the read address sequencer and for transmitting the sequence of data signals read from the memory.
Claim 10
Dependent Claim
261 words
A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising: a write address input port including a single lead for serially receiving a start write address for a sequence of memory access operations; a write address sequencer, connected to the write address input port and responsive to the start write address and a first clock signal, for generating a sequence of memory write addresses, commencing with the start write address, which are applied to the decoder, the write address sequencer being arranged to increment sequential ones of the memory write addresses by a variable offset value; a data input port for receiving a sequence of data signals and for loading the received data signals sequentially into the memory addresses generated by the write address sequencer; a read address input port including a single lead for serially receiving a start read address for a sequence of memory access operations; a read address sequencer, connected to the read address input port and responsive to the start read address and a second clock signal, for generating a sequence of memory read addresses, commencing with the start read address, which are applied to the decoder, the read address sequencer being arranged to increment sequential ones of the memory read addresses by a variable offset value; and a data output port arranged for receiving a sequence of data signals read from the memory addresses generated by the read address sequencer and for transmitting the sequence of data signals read from the memory.
Claim 11
Dependent Claim
29 words
A semiconductor memory chip, in accordance with claim 7, wherein the offset value for the write address sequencer is different than the offset value for the read address sequencer.
Claim 12
Dependent Claim
127 words
A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising: a read address input port including a single lead for serially receiving bits of a start read address for a sequence of memory access operations; a read address sequencer, connected to the read address input port and responsive to the start read address and a clock signal, for generating a sequence of memory read addresses, commencing with the start read address, which are applied to the decoder; and a data output port arranged for receiving a sequence of data signals read from the memory addresses generated by the read address sequencer and for transmitting the sequence of data signals read from the memory.
Claim 13
Dependent Claim
127 words
A semiconductor memory chip including cells, arranged in rows and columns and addressed by addresses applied to a decoder, the semiconductor memory chip comprising: a read address input port including a single lead for serially receiving bits of a start read address for a sequence of memory access operations; a read address sequencer, connected to the read address input port and responsive to the start read address and a clock signal, for generating a sequence of memory read addresses, commencing with the start read address, which are applied to the decoder; and a data output port arranged for receiving a sequence of data signals read from the memory addresses generated by the read address sequencer and for transmitting the sequence of data signals read from the memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-20 | 1998-09-19 | 1999-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-20 | 2002-09-19 | 2003-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-20 | 2006-09-19 | 2007-03-21 | $7700.00 | Window Closed / Lapsed |