Integrated circuit that supports and method for wafer-level testing

Claim 2

An integrated circuit that is formed on a die that is formed as a detachable part of a wafer, said wafer including both a wafer test-mode path that is operable to carry a wafer test-mode signal and a wafer power-supply path that is operable to carry a wafer power-supply voltage, the integrated circuit comprising: functional circuitry having a normal mode of operation and a wafer test mode of operation, said functional circuitry coupled to said wafer test-mode path before said die is detached from said wafer, said functional circuitry operable to function in said wafer test mode of operation when said wafer test-mode signal has a first state; and a wafer test-mode power circuit that is coupled to said functional circuitry and that is coupled to said wafer power-supply path and said wafer test-mode path before said die is detached from said wafer, said power circuit operable to couple said wafer power-supply path to said functional circuitry when said wafer test-mode signal has said first state.

Claim 3

The integrated circuit of claim 1 wherein said wafer test-mode power circuit is operable to uncouple said wafer power-supply path from said functional circuitry when said wafer test-mode signal has a second state.

Claim 4

The integrated circuit of claim 1 wherein said functional circuitry is operable to function in said normal mode of operation when said wafer test-mode signal has a second state.

Claim 5

The integrated circuit of claim 1, further comprising: a substrate of semiconductor material, a portion of said substrate biased to a first voltage that is unequal to said wafer power-supply voltage; said wafer test-mode power circuit operable to uncouple said wafer power-supply path from said functional circuitry when said wafer test-mode signal has a second state; said functional circuitry operable to function in said normal mode of operation when said wafer test-mode signal has said second state; and said second state of said wafer test-mode signal having a voltage level that is substantially equal to said first voltage.

Claim 6

The integrated circuit of claim 1 wherein said functional circuitry comprises a memory circuit.

Claim 7

An integrated circuit that is formed on a die that is formed as a detachable part of a wafer, said wafer including a wafer test-mode path that is operable to carry a wafer test-mode signal and first and second wafer power-supply paths that are operable to respectively carry first and second wafer power-supply voltages, the integrated circuit comprising: functional circuitry having a normal mode of operation and a wafer test mode of operation, said functional circuitry having a wafer test-mode input terminal that is coupled to said wafer test-mode path before said die is detached from said wafer, said functional circuitry coupled to said first wafer power-supply path before said die is detached from said wafer, said functional circuitry operable to function in said wafer test mode of operation when said wafer test-mode signal has a first state; and a wafer test-mode power circuit that is coupled to said functional circuitry and that is coupled to said first and second wafer power-supply paths and to said wafer test-mode path before said die is detached from said wafer, said power circuit operable to couple said second wafer power-supply path to said functional circuitry when said wafer test-mode signal has said first state.

Claim 8

An integrated circuit that is formed on a die that is formed as a detachable part of a wafer, said wafer including a wafer test-mode path that is operable to carry a wafer test-mode signal and first and second wafer power-supply paths that are operable to respectively carry first and second wafer power-supply voltages, the integrated circuit comprising: functional circuitry having a normal mode of operation and a wafer test mode of operation, said functional circuitry having a wafer test-mode input terminal that is coupled to said wafer test-mode path before said die is detached from said wafer, said functional circuitry coupled to said first wafer power-supply path before said die is detached from said wafer, said functional circuitry operable to function in said wafer test mode of operation when said wafer test-mode signal has a first state; and a wafer test-mode power circuit that is coupled to said functional circuitry and that is coupled to said first and second wafer power-supply paths and to said wafer test-mode path before said die is detached from said wafer, said power circuit operable to couple said second wafer power-supply path to said functional circuitry when said wafer test-mode signal has said first state.

Claim 9

The integrated circuit of claim 6, further comprising: a first fuse element that is coupled between said first wafer power-supply path and both of said functional circuitry and said wafer test-mode power circuit; a second fuse element that is coupled between said second power-supply path and said wafer test-mode power circuit; and a third fuse element that is coupled between said wafer test-mode path and both of said functional circuitry and said wafer test-mode power circuit.

Claim 10

The integrated circuit of claim 6, further comprising: a substrate of semiconductor material, a portion of said substrate biased to approximately said a first wafer power-supply voltage; said wafer test-mode power circuit operable to uncouple said wafer power-supply path from said functional circuitry when said wafer test-mode signal has a second state; and said second state of said wafer test-mode signal having a voltage level that is approximately equal to said first wafer power-supply voltage.

Claim 11

The integrated circuit of claim 6, further comprising: a substrate of semiconductor material, a portion of said substrate biased to approximately said a first wafer power-supply voltage; said wafer test-mode power circuit operable to uncouple said wafer power-supply path from said functional circuitry when said wafer test-mode signal has a second state; said functional circuitry operable to function in said normal mode of operation when said wafer test-mode signal has said second state; and said second state of said wafer test-mode signal having a voltage level that is approximately equal to said first wafer power-supply voltage.

Claim 12

The integrated circuit of claim 6, further comprising: a first power-supply node coupled to said first wafer power-supply path before said die is detached from said wafer; a latch circuit coupled to said wafer test-mode input terminal of said functional circuitry, said latch circuit operable to maintain said wafer test-mode input terminal at a first voltage after said die is detached from said wafer, said first voltage approximately equal to said first wafer power-supply voltage; a coupling circuit coupled between said first power-supply node and said latch circuit, said switch operable to uncouple said latch circuit from said first power-supply node when said wafer test-mode signal has said first state; and a load coupled between said wafer test-mode input terminal and said first wafer power-supply path before said die is detached from said wafer.

Claim 13

The integrated circuit of claim 6, further comprising: a first power-supply node coupled to said first wafer power-supply path before said die is detached from said wafer; a latch circuit coupled to said wafer test-mode input terminal of said functional circuitry, said latch circuit operable to maintain said wafer test-mode input terminal at a first voltage after said die is detached from said wafer, said first voltage approximately equal to said first wafer power-supply voltage; a coupling circuit coupled between said first power-supply node and said latch circuit, said switch operable to uncouple said latch circuit from said first power-supply node before said die is detached from said wafer; and a load coupled between said wafer test-mode input terminal and said first power-supply node.

Claim 14

The integrated circuit of claim 6, further comprising: a first power-supply node coupled to said first wafer power-supply path before said die is detached from said wafer; a latch circuit coupled to said wafer test-mode input terminal of said functional circuitry, said latch circuit having an on resistance and operable to maintain said wafer test-mode input terminal at a first voltage after said die is detached from said wafer, said first voltage approximately equal to said first wafer power-supply voltage; a coupling circuit coupled between said first power-supply node and said latch circuit, said switch operable to uncouple said latch circuit from said first power-supply node before said die is detached from said wafer; and a polysilicon load resistor coupled between said wafer test-mode input terminal and said first power-supply node, said load resistor having a resistance that is significantly greater than said on resistance of said latch circuit.

Claim 15

An integrated circuit that is formed on a die that is formed as a removable portion of a wafer, said wafer including a wafer-test-mode-signal path and first and second wafer supply paths, the integrated circuit comprising: a first supply node that is directly coupled to said first wafer supply path while said die is part of said wafer; a second supply node that is directly coupled to said second wafer supply path while said die is part of said wafer; an isolatable supply node; a signal node that is directly coupled to said wafer-test-mode-signal path while said die is part of said wafer; a functional circuit that is coupled to said signal node and to said first and isolatable supply nodes; and a switch circuit that is coupled between said second and isolatable supply nodes, said switch circuit having a first switch-path terminal that is coupled to said second supply node, a second switch-path terminal that is coupled to said isolatable supply node, and a control terminal that is coupled to said signal node.

Claim 16

An integrated circuit that is formed on a die that is formed as a removable portion of a wafer, said wafer including a wafer-test-mode-signal path and first and second wafer supply paths, the integrated circuit comprising: a first supply node that is directly coupled to said first wafer supply path while said die is part of said wafer; a second supply node that is directly coupled to said second wafer supply path while said die is part of said wafer; an isolatable supply node; a signal node that is directly coupled to said wafer-test-mode-signal path while said die is part of said wafer; a functional circuit that is coupled to said signal node and to said first and isolatable supply nodes; and a switch circuit that is coupled between said second and isolatable supply nodes, said switch circuit having a first switch-path terminal that is coupled to said second supply node, a second switch-path terminal that is coupled to said isolatable supply node, and a control terminal that is coupled to said signal node.

Claim 17

The integrated circuit of claim 13, further comprising a substrate of semiconductor material, at least a portion of said substrate coupled to said first supply node.

Claim 18

The integrated circuit of claim 13 wherein said switch circuit comprises: a signal-inversion circuit that has both an input terminal coupled to said control terminal and an output terminal; a first type of transistor that is coupled between said first and second switch-path terminals and that has a control terminal coupled to said output terminal of said signal-inversion circuit; and a second type of transistor that is coupled between said first and second switch-path terminals and that has a control terminal coupled to said control terminal of said switch circuit.

Claim 19

The integrated circuit of claim 13, further comprising: a substrate of n-type semiconductor material, at least one portion of said substrate coupled to said first supply node; and said switch circuit comprising, a signal-inversion circuit that has both an input terminal coupled to said control terminal and an output terminal, an n-channel transistor that is coupled between said first and second switch-path terminals and that has a gate terminal coupled to said output terminal of said signal-inversion circuit, and a p-channel transistor that is coupled between said first and second switch-path terminals and that has a gate terminal coupled to said control terminal of said switch circuit.

Claim 20

The integrated circuit of claim 13, further comprising: a substrate of p-type semiconductor material, at least one portion of said substrate coupled to said first supply node; and said switch circuit comprising, a signal-inversion circuit that has both an input terminal coupled to said control terminal and an output terminal, a p-channel transistor that is coupled between said first and second switch-path terminals and that has a gate terminal coupled to said output terminal of said signal-inversion circuit, and an n-channel transistor that is coupled between said first and second switch-path terminals and that has a gate terminal coupled to said control terminal of said switch circuit.

Claim 21

The integrated circuit of claim 13, further comprising a latch circuit having a power terminal that is coupled to said first supply node and having an output terminal that is coupled to said signal node.

Claim 22

The integrated circuit of claim 13, further comprising: an intermediate supply node that is coupled to said first supply node after said die has been removed from said wafer; a latch circuit having a power terminal that is coupled to said intermediate supply node and having an output terminal that is coupled to said signal node, said latch circuit having an output impedance; and a load that is coupled between said signal node and said first supply node, said load having an impedance that is significantly greater than said output impedance of said latch circuit.

Claim 23

The integrated circuit of claim 13, further comprising: an intermediate supply node that is coupled to said first supply node after said die has been removed from said wafer; a reset node; a latch circuit having a power terminal that is coupled to said intermediate supply node, an output terminal that is coupled to said signal node, and a reset terminal that is coupled to reset node, said latch circuit having an output impedance; and a load that is coupled between said signal node and said first supply node, said load having an impedance that is significantly greater than said output impedance of said latch circuit.

Claim 24

The integrate circuit of claim 13, further comprising: an intermediate supply node that is coupled to said first supply node after said die has been removed from said wafer; a reset node; a first transistor of a first type coupled between said intermediate supply node and said signal node, said first transistor having a control terminal coupled to said reset node; an inverter circuit having an input terminal coupled to said signal node and having an output terminal; a second transistor of said first type coupled between said intermediate supply node and said signal node, said second transistor having a control terminal coupled to said output terminal of said inverter circuit, said second transistor having an on impedance; and a load that is coupled between said signal node and said first supply node, said load having an impedance that is significantly greater than said on impedance of said second transistor.

Claim 25

The integrated circuit of claim 13, further comprising: an intermediate supply node that is coupled to said first supply node after said die has been removed from said wafer; a latch circuit having a power terminal and having an output terminal that is coupled to said signal node, said latch circuit having an output impedance; a switch coupled between said intermediate supply node and said power terminal of said latch circuit, said switch having a control terminal coupled to said signal node; and a load that is coupled between said signal node and said first supply node, said load having an impedance that is significantly greater than said output impedance of said latch circuit.

Claim 26

A memory device that is formed on a die that is formed as part of a wafer, said wafer including both a wafer test-mode path that is operable to carry a wafer test-mode signal and a wafer supply path that is operable to carry a wafer supply voltage, the memory device comprising: a supply node that is directly coupled to said wafer supply path while said die forms said part of said wafer; an isolatable supply node; a signal node that is directly coupled to said wafer-test-mode-signal path while said die forms said part of said wafer; an array of memory cells that is coupled to said signal node and to said isolatable supply node; an address decoder that is coupled to said array, said signal node, and said isolatable supply node, said address decoder operable to select an addressed one of said memory cells; an address buffer that is coupled to said address decoder, said signal node, and said isolatable supply node, said address buffer operable to control said address decoder; a data buffer that is coupled to said array of memory cells, said signal node, and said isolatable supply node, said data buffer operable to read data from and write data to said array; said address and data buffers each having a normal mode of operation and a wafer test mode of operation, said address and data buffers each operable to function in said respective wafer test mode of operation when said wafer test-mode signal has a first state; and a wafer test-mode power circuit that is coupled to said signal node and to said isolatable supply node, said power circuit coupled to said wafer power-supply path while said die forms said part of said wafer, said power circuit operable to couple said wafer power-supply path to said isolatable supply node when said wafer test-mode signal has said first state.

Claim 27

A memory device that is formed on a die that is formed as part of a wafer, said wafer including both a wafer test-mode path that is operable to carry a wafer test-mode signal and a wafer supply path that is operable to carry a wafer supply voltage, the memory device comprising: a supply node that is directly coupled to said wafer supply path while said die forms said part of said wafer; an isolatable supply node; a signal node that is directly coupled to said wafer-test-mode-signal path while said die forms said part of said wafer; an array of memory cells that is coupled to said signal node and to said isolatable supply node; an address decoder that is coupled to said array, said signal node, and said isolatable supply node, said address decoder operable to select an addressed one of said memory cells; an address buffer that is coupled to said address decoder, said signal node, and said isolatable supply node, said address buffer operable to control said address decoder; a data buffer that is coupled to said array of memory cells, said signal node, and said isolatable supply node, said data buffer operable to read data from and write data to said array; said address and data buffers each having a normal mode of operation and a wafer test mode of operation, said address and data buffers each operable to function in said respective wafer test mode of operation when said wafer test-mode signal has a first state; and a wafer test-mode power circuit that is coupled to said signal node and to said isolatable supply node, said power circuit coupled to said wafer power-supply path while said die forms said part of said wafer, said power circuit operable to couple said wafer power-supply path to said isolatable supply node when said wafer test-mode signal has said first state.

Claim 28

The memory device of claim 23 wherein: said wafer test-mode power circuit is operable to uncouple said wafer power-supply path from said isolatable supply node when said wafer test-mode signal has a second state; and said address and data buffers are each operable to function in said respective normal mode of operation when said wafer test-mode signal has said second state.

Claim 29

The memory device of claim 23, further comprising: a substrate of semiconductor material, a portion of said substrate biased to a first voltage level that is unequal to said wafer power-supply voltage; said wafer test-mode power circuit operable to uncouple said wafer power-supply path from said isolatable supply node when said wafer test-mode signal has a second state; said address and data buffers each operable to function in said respective normal mode of operation when said wafer test-mode signal has said second state; and said second state of said wafer test-mode signal having a voltage level that is substantially equal to said first voltage level.

Claim 30

A computer system, comprising: a data input device; a data output device; computing circuitry that is coupled to said data input and output devices, said computing circuitry including a memory circuit that is formed on a die that is formed as a portion of a wafer, said wafer including both a wafer test-mode path that is operable to carry a wafer test-mode signal and a wafer power-supply path that is operable to carry a wafer power-supply voltage, the memory circuit including, a supply node that is directly coupled to said wafer supply path while said die forms said portion of said wafer, an isolatable supply node; a signal node that is directly coupled to said wafer-test-mode-signal path while said die forms said portion of said wafer, an array of memory cells that is coupled to said signal node and to said isolatable supply node, an address decoder that is coupled to said array, said signal node, and said isolatable supply node, said address decoder operable to select an addressed one of said memory cells, an address buffer that is coupled to said address decoder, said signal node, and said isolatable supply node, said address buffer operable to control said address decoder, a data buffer that is coupled to said array of memory cells, said signal node, and said isolatable supply node, said data buffer operable to read data from and write data to said array, said address and data buffers each having a normal mode of operation and a wafer test mode of operation, said address and data buffers each operable to function in said respective wafer test mode of operation when said wafer test-mode signal has a first state, and a wafer test-mode power circuit that is coupled to said signal node and to said isolatable supply node, said power circuit coupled to said wafer power-supply path while said die forms said portion of said wafer, said power circuit operable to couple said wafer power-supply path to said isolatable supply node when said wafer test-mode signal has said first state.

Claim 31

A computer system, comprising: a data input device; a data output device; computing circuitry that is coupled to said data input and output devices, said computing circuitry including a memory circuit that is formed on a die that is formed as a portion of a wafer, said wafer including both a wafer test-mode path that is operable to carry a wafer test-mode signal and a wafer power-supply path that is operable to carry a wafer power-supply voltage, the memory circuit including, a supply node that is directly coupled to said wafer supply path while said die forms said portion of said wafer, an isolatable supply node; a signal node that is directly coupled to said wafer-test-mode-signal path while said die forms said portion of said wafer, an array of memory cells that is coupled to said signal node and to said isolatable supply node, an address decoder that is coupled to said array, said signal node, and said isolatable supply node, said address decoder operable to select an addressed one of said memory cells, an address buffer that is coupled to said address decoder, said signal node, and said isolatable supply node, said address buffer operable to control said address decoder, a data buffer that is coupled to said array of memory cells, said signal node, and said isolatable supply node, said data buffer operable to read data from and write data to said array, said address and data buffers each having a normal mode of operation and a wafer test mode of operation, said address and data buffers each operable to function in said respective wafer test mode of operation when said wafer test-mode signal has a first state, and a wafer test-mode power circuit that is coupled to said signal node and to said isolatable supply node, said power circuit coupled to said wafer power-supply path while said die forms said portion of said wafer, said power circuit operable to couple said wafer power-supply path to said isolatable supply node when said wafer test-mode signal has said first state.

Claim 32

The computer system of claim 26, further comprising: a data storage device coupled to said computing circuitry; and said computing circuitry including a processor that is coupled to said memory device.

Claim 33

The computer system of claim 26 wherein: said wafer test-mode power circuit is operable to uncouple said wafer power-supply path from said isolatable supply node when said wafer test-mode signal has a second state; and said address and data buffers are each operable to function in said respective normal mode of operation when said wafer test-mode signal has said second state.

Claim 34

The computer system of claim 26 wherein said memory device further comprises: a substrate of semiconductor material, a portion of said substrate biased to a first voltage level that is unequal to said wafer power-supply voltage; said wafer test-mode power circuit operable to uncouple said wafer power-supply path from said isolatable supply node when said wafer test-mode signal has a second state; said address and data buffers each operable to function in said respective normal mode of operation when said wafer test-mode signal has said second state; and said second state of said wafer test-mode signal having a voltage level that is substantially equal to said first voltage level.

Claim 35

A wafer of semiconductor material, the wafer comprising: a plurality of dies; a scribe line that is disposed between said dies; a wafer-test-mode-signal path that is disposed on said scribe line and coupled to each of said dies; first and second wafer supply paths that are disposed on said scribe line and coupled to each of said dies; each of said dies comprising, a first supply node that is coupled to said first wafer supply path; a second supply node that is coupled to said second wafer supply path wafer; an isolatable supply node; a signal node that is coupled to said wafer-test-mode-signal path; circuitry that is coupled to said signal node and to said first and isolatable supply nodes; and a switch circuit that is coupled between said second and isolatable supply nodes, said switch circuit having a first switch-path terminal that is coupled to said second supply node, a second switch-path terminal that is coupled to said isolatable supply node, and a control terminal that is coupled to said signal node.

Claim 36

A wafer of semiconductor material, the wafer comprising: a plurality of dies; a scribe line that is disposed between said dies; a wafer-test-mode-signal path that is disposed on said scribe line and coupled to each of said dies; first and second wafer supply paths that are disposed on said scribe line and coupled to each of said dies; each of said dies comprising, a first supply node that is coupled to said first wafer supply path; a second supply node that is coupled to said second wafer supply path wafer; an isolatable supply node; a signal node that is coupled to said wafer-test-mode-signal path; circuitry that is coupled to said signal node and to said first and isolatable supply nodes; and a switch circuit that is coupled between said second and isolatable supply nodes, said switch circuit having a first switch-path terminal that is coupled to said second supply node, a second switch-path terminal that is coupled to said isolatable supply node, and a control terminal that is coupled to said signal node.

Claim 37

The wafer of claim 30 wherein each of said dies comprises a substrate formed from said semiconductor material, a portion of said substrate coupled to said first supply node.

Claim 38

The wafer of claim 30 wherein said switch circuit comprises: a signal-inversion circuit that has both an input terminal coupled to said control terminal and an output terminal; a first type of transistor that is coupled between said first and second switch-path terminals and that has a control terminal coupled to said output terminal of said signal-inversion circuit; and a second type of transistor that is coupled between said first and second switch-path terminals and that has a control terminal coupled to said control terminal of said switch circuit.

Claim 39

The wafer of claim 30 wherein each of said dies further comprises: an intermediate supply node that is operable to be coupled to said first supply node after said each die has been removed from said wafer; a latch circuit having a power terminal that is coupled to said intermediate supply node and having an output terminal that is coupled to said signal node, said latch circuit having an output impedance; and a load that is coupled between said signal node and said first supply node, said load having an impedance that is significantly greater than said output impedance of said latch circuit.

Claim 40

The wafer of claim 30 wherein each of said dies further comprises: an intermediate supply node that is operable to be coupled to said first supply node after said die has been removed from said wafer; a reset node; a latch circuit having a power terminal that is coupled to said intermediate supply node, an output terminal that is coupled to said signal node, and a reset terminal that is coupled to reset node, said latch circuit having an output impedance; and a load that is coupled between said signal node and said first supply node, said load having an impedance that is significantly greater than said output impedance of said latch circuit.

Claim 43

The method of claim 35, further comprising: testing said dies for defects before said coupling; and uncoupling said power conductive path from those of said circuits that are on defective ones of said dies.

Claim 44

The method of claim 35, further comprising causing each of said circuits to operate in a normal mode while said wafer test signal has a second state.