US5459688A
Expired / Lapsed
US
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Semiconductor memory cell and fabrication process
Assignee: Motorola Solutions Inc
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Filing: 1994-05-17
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Granted: 1995-10-17
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Expires: 2014-05-17
Abstract
Abstract A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) overlie a single-crystal semiconductor substrate (12) and the channel region (46) of each driver transistor overlies a portion of an adjacent wordline. A portion of the thin-film layer (36, 36') makes contact to the single-crystal semiconductor substrate (12) adjacent to the opposite wordline. The channel and source-drain regions of first and second load transistors (15, 21) are formed in a second thin-film layer (64) which overlies the driver transistors (13, 19). The load transistors (15, 21) are cross-coupled to the driver transistors (13, 19) through common nodes (31, 33).
Inventors
- 👤 James R. Pfiester
- 👤 James D. Hayden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:57
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10D; H10D86/00; H10D86/201; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
85 words
A semiconductor memory cell comprising: a single-crystal semiconductor substrate; first and second parallel opposed wordlines overlying the substrate; and first and second cross-coupled driver transistors overlying the first and second wordlines respectively, wherein each driver transistor includes a first thin-film layer having a source-drain region and a channel region formed therein, and wherein the channel region of the first driver transistor overlies a portion of the first wordline. and wherein the channel region of the second driver transistor overlies a portion of the second wordline.
Claim 2
Dependent Claim
85 words
A semiconductor memory cell comprising: a single-crystal semiconductor substrate; first and second parallel opposed wordlines overlying the substrate; and first and second cross-coupled driver transistors overlying the first and second wordlines respectively, wherein each driver transistor includes a first thin-film layer having a source-drain region and a channel region formed therein, and wherein the channel region of the first driver transistor overlies a portion of the first wordline. and wherein the channel region of the second driver transistor overlies a portion of the second wordline.
Claim 3
Dependent Claim
142 words
The semiconductor memory cell of claim 1 further comprising: a first Vss interconnect layer overlying and electrically insulated from the thin-film layer of the first driver transistor; a second Vss interconnect layer overlying and electrically insulated from the thin-film layer of the second driver transistor; a first bit-line interconnect layer overlying a portion of the first wordline and electrically insulated from the first wordline; a second bit-line interconnect layer overlying a portion of the second wordline and electrically insulated from the second wordline; a first load transistor overlying the first driver transistor, the first load transistor having a second thin-film layer electrically contacting the first thin-film layer of the first driver transistor; and a second load transistor overlying the second driver transistor, the second load transistor having a second thin-film layer electrically contacting the first thin-film layer of the first driver transistor.
Claim 4
Dependent Claim
104 words
A semiconductor memory cell comprising: a semiconductor substrate having a surface; an isolation region in the substrate defining an active region on the substrate surface; a dielectric layer overlying the active region; a first and second parallel opposed wordlines, the first wordline overlying a portion of the active region and the second wordline overlying the isolation region; a contact opening in the dielectric layer intermediate to the first and second wordlines; and a driver transistor overlying a portion of the second wordline, wherein the channel of the driver transistor overlies the second wordline and contacts the substrate through the opening in the dielectric layer.
Claim 5
Dependent Claim
104 words
A semiconductor memory cell comprising: a semiconductor substrate having a surface; an isolation region in the substrate defining an active region on the substrate surface; a dielectric layer overlying the active region; a first and second parallel opposed wordlines, the first wordline overlying a portion of the active region and the second wordline overlying the isolation region; a contact opening in the dielectric layer intermediate to the first and second wordlines; and a driver transistor overlying a portion of the second wordline, wherein the channel of the driver transistor overlies the second wordline and contacts the substrate through the opening in the dielectric layer.
Claim 6
Dependent Claim
26 words
The semiconductor device of claim 3 further comprising a Vss interconnect layer overlying the driver transistor and electrically coupled to the channel of the driver transistor.
Claim 7
Dependent Claim
153 words
A semiconductor memory cell comprising: a single-crystal substrate having an active region and an isolation region; first and second wordlines wherein the first wordline overlies the active region and the second wordline overlies the isolation region; a first dielectric layer overlying the active region, the dielectric layer having an opening adjacent to the first wordline exposing a portion of the single-crystal substrate; a first thin-film layer having a first portion overlying the second wordline and a second portion in contact with the single-crystal substrate through the opening in the dielectric layer and a third portion overlying a portion of the first wordline; a second dielectric layer overlying the first thin-film layer; a driver-gate electrode overlying the first portion of the first thin-film layer and separated from the first thin-film layer by the second dielectric layer; and first source and drain regions in the first thin-film layer on either side of the driver-gate electrode.
Claim 8
Dependent Claim
153 words
A semiconductor memory cell comprising: a single-crystal substrate having an active region and an isolation region; first and second wordlines wherein the first wordline overlies the active region and the second wordline overlies the isolation region; a first dielectric layer overlying the active region, the dielectric layer having an opening adjacent to the first wordline exposing a portion of the single-crystal substrate; a first thin-film layer having a first portion overlying the second wordline and a second portion in contact with the single-crystal substrate through the opening in the dielectric layer and a third portion overlying a portion of the first wordline; a second dielectric layer overlying the first thin-film layer; a driver-gate electrode overlying the first portion of the first thin-film layer and separated from the first thin-film layer by the second dielectric layer; and first source and drain regions in the first thin-film layer on either side of the driver-gate electrode.
Claim 9
Dependent Claim
28 words
The semiconductor memory cell of claim 5 wherein the first thin-film layer is a material selected from the group consisting of single-crystal silicon, epitaxial silicon, and polycrystalline silicon.
Claim 10
Dependent Claim
132 words
The semiconductor memory cell of claim 6 further comprising: a Vss interconnect layer electrically isolated from the driver-gate electrode and the second wordline and overlying the driver-gate electrode and extending over a portion of the isolation region; a bit-line interconnect layer overlying the first wordline and extending over a portion of the active region; an insulation layer overlying the interconnect layer; a second silicon layer overlying the first portion of the interconnect layer and separated from the interconnect layer by the insulation layer; a third dielectric layer overlying the second silicon layer; a second gate electrode overlying the second silicon layer and separated from the second silicon layer by the third dielectric layer; and second source and drain regions in the second silicon layer on either side of the second gate electrode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-16 | 1999-04-17 | 1999-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-16 | 2003-04-17 | 2003-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-16 | 2007-04-17 | 2007-10-17 | $7700.00 | Window Closed / Lapsed |