Semiconductor memory cell having a trench structure

Claim 2

A semiconductor memory device comprising: a substrate having a surface; a well region in the substrate; a trench in the substrate, the trench having a bottom surface and a wall surface and a central region; an inverter in the trench, the inverter having a first channel region of a first conductivity type in the wall surface, a second channel region of a second conductivity type in the central region extending from the bottom surface to substrate surface, and a toroidal shared-gate electrode intermediate to the first and second channel regions; a first buried layer in the substrate electrically coupled to the second channel region at the bottom surface of the trench; and a second buried layer in the substrate intermediate to the well region and the first buried layer and electrically coupled to the first channel region, wherein the first buried layer provides a first logic signal to the first channel region and the second buried layer provides a second logic signal to the second channel region.

Claim 3

The semiconductor memory device of claim 1 further comprising a wordline overlying a portion of the well region and separated therefrom by a gate dielectric layer, the wordline providing electrical control to an underlying portion of the well region for electrically coupling a bit-line signal to the second channel region of the inverter.

Claim 4

The semiconductor memory device of claim 1, wherein the second channel region comprises a thin-film layer having a source region at the bottom surface of the trench, a drain region extending outward from the trench, the drain region overlying a portion of the well region adjacent to the trench and contacting the well region.

Claim 5

The semiconductor memory device of claim 1, wherein the first channel region comprises: a source region defined by a portion of the second buried layer along the wall surface of the trench; a drain region defined by a doped region in the well region surrounding the trench at the substrate surface; and a channel region along the wall surface of the trench intermediate to the source region and the drain region.

Claim 6

A semiconductor memory device comprising: a substrate having a well region; a trench in the well region having a wall surface and a bottom surface; a first channel region formed in the substrate along the wall surface of the trench; a first upper drain region and a first lower source region in the substrate on either side of the first channel region; a shared gate electrode overlying the wall surface and a portion of the bottom surface and separated from the wall surface and the bottom surface by a first dielectric layer; a thin-film layer filling a central portion of the trench and isolated from the shared gate electrode by a second dielectric layer; a second channel region in the thin-film layer; a second upper drain region and a second lower source region in the thin-film layer on either side of the second channel region, wherein the second lower source region contacts the substrate at the bottom surface of the trench; a first buried region in the substrate contacting the second lower source region at the bottom of the trench; and a second buried region in the substrate contacting the first lower source region, wherein a first logic signal is provided to the thin-film layer by the first buried region and a second logic signal is provided to the first lower source region by the second buried region.

Claim 7

A semiconductor memory device comprising: a substrate having a well region; a trench in the well region having a wall surface and a bottom surface; a first channel region formed in the substrate along the wall surface of the trench; a first upper drain region and a first lower source region in the substrate on either side of the first channel region; a shared gate electrode overlying the wall surface and a portion of the bottom surface and separated from the wall surface and the bottom surface by a first dielectric layer; a thin-film layer filling a central portion of the trench and isolated from the shared gate electrode by a second dielectric layer; a second channel region in the thin-film layer; a second upper drain region and a second lower source region in the thin-film layer on either side of the second channel region, wherein the second lower source region contacts the substrate at the bottom surface of the trench; a first buried region in the substrate contacting the second lower source region at the bottom of the trench; and a second buried region in the substrate contacting the first lower source region, wherein a first logic signal is provided to the thin-film layer by the first buried region and a second logic signal is provided to the first lower source region by the second buried region.

Claim 8

The semiconductor memory device of claim 5, wherein the second upper drain region extends out of the trench and contacts the first upper drain region.

Claim 9

The semiconductor memory device of claim 5 further comprising a wordline overlying a portion of the well region adjacent to the trench defining an access transistor, wherein the access transistor provides a bit-line signal to the first upper drain region.

Claim 10

A semiconductor memory device comprising: a semiconductor substrate; first and second opposed well regions in the substrate; a first trench in the first well region and a second trench in the second well region, each trench having a bottom surface, a wall surface, and a central region; an inverter in each trench, each inverter having a toroidal shared-gate electrode, a thin-film load transistor in the central portion of the trench and a driver transistor in the wall surface of the trench; a first cell interconnect integral with the shared-gate electrode of the first inverter, extending away from the first well region and electrically coupled to the second well region; a second cell interconnect integral with the shared-gate electrode of the second inverter, extending away from the second well region and electrically coupled to the first well region; a first buried layer of a first conductivity type in the substrate in contact with the thin-film load transistor at the bottom surface of each trench; and a second buried layer of a second conductivity type underlying the first and second well regions and contacting the wall surface of the first and second trenches, wherein the first buried layer provides a first logic signal to the thin-film load transistor and the second buried layer provides a second logic signal to the driver transistor.

Claim 11

A semiconductor memory device comprising: a semiconductor substrate; first and second opposed well regions in the substrate; a first trench in the first well region and a second trench in the second well region, each trench having a bottom surface, a wall surface, and a central region; an inverter in each trench, each inverter having a toroidal shared-gate electrode, a thin-film load transistor in the central portion of the trench and a driver transistor in the wall surface of the trench; a first cell interconnect integral with the shared-gate electrode of the first inverter, extending away from the first well region and electrically coupled to the second well region; a second cell interconnect integral with the shared-gate electrode of the second inverter, extending away from the second well region and electrically coupled to the first well region; a first buried layer of a first conductivity type in the substrate in contact with the thin-film load transistor at the bottom surface of each trench; and a second buried layer of a second conductivity type underlying the first and second well regions and contacting the wall surface of the first and second trenches, wherein the first buried layer provides a first logic signal to the thin-film load transistor and the second buried layer provides a second logic signal to the driver transistor.

Claim 12

The semiconductor memory device of claim 8 further comprising: wordline overlying a portion of the first well region and a portion of the second well region, wherein the wordline defines a first access transistor in the first well region and a second transistor in the second well region.

Claim 13

The semiconductor memory device of claim 9 further comprising a conductive bit-line contact land overlying and electrically isolated from a portion of the wordline, wherein the contact land contacts a portion of the well region adjacent to the wordline.

Claim 14

The semiconductor memory device of claim 9, wherein the first cell interconnect contacts a portion of the thin-film load transistor in the second well region, and wherein the second cell interconnect contacts a portion of the thin-film load transistor in the first well region.

Claim 15

The semiconductor memory device of claim 9, wherein the first cell interconnect contacts a portion of the second well region intermediate to the second trench and the wordline, and wherein the second cell interconnect contacts a portion of the first well region intermediate to the first trench and the wordline.

Claim 16

The semiconductor memory device of claim 8 further comprising: first and second parallel opposed wordlines, wherein the first wordline overlies a portion of the first well region and extends to the second well region and overlies a portion of the thin-film load transistor in the second trench, and wherein the second wordline overlies a portion of the second well region and extends to the first well region and overlies a portion of the thin-film load transistor in the first trench.

Claim 17

The semiconductor memory device of claim 13, wherein the first cell interconnect contacts a portion of the second well region intermediate to the second trench and the first wordline, and wherein the second cell interconnect contacts a portion of the first well region intermediate to the first trench and the second wordline.

Claim 18

The semiconductor memory device of claim 13 further comprising: a first conductive bit-line contact land overlying and electrically isolated from a portion of the first wordline, wherein the contact land contacts a portion of the first well region adjacent to the first wordline; and a second conductive bit-line contact land overlying and electrically isolated from a portion of the second wordline, wherein the contact land contacts a portion of the second well region adjacent to the second wordline.