US5198683A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit memory device and structural layout thereof
Assignee: NXP USA Inc
•
Filing: 1991-05-03
•
Granted: 1993-03-30
•
Expires: 2011-05-03
Abstract
Abstract A memory cell layout achieves a reduced cell area. In one embodiment, a six transitor (6T) SRAM cell has two vertical thin-film transistors (18 and 20) as load transistors, two transfer transistors (10 and 12), two latch transistors (14 and 16), and two storage nodes. NODE 1 and NODE 2 of the cell each have a minimum feature defined by trenches (60). Four of five interconnects associated with each node are located within the respective trench. For example in NODE 1, a drain of latch transistor (14), a gate of latch transistor (16), a drain of load transistor (18), and a current electrode of transfer transistor (10) are electrically coupled within or beneath one trench (60). A remaining interconnection of NODE 1, a gate of load transistor 20, is located within the trench associated with NODE 2. Thus, ten interconnects of the memory cell are contained within areas defined by two minimum features.
Inventors
- 👤 Richard D. Sivan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:37
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6728; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
258 words
An integrated circuit memory device having a plurality of cells, each cell comprising: first and second latch transistors, each latch transistor having a control electrode and first and second current electrodes; first and second transfer transistors, each transfer transistor having a control electrode and first and second current electrodes; first and second vertical load transistors, each load transistor being positioned within a substantially vertical wall trench and having a first current electrode located adjacent a bottom surface of the trench, a second current electrode, a channel region along the substantially vertical wall of the trench which connects the first and second current electrodes, and a control electrode contained within the trench; a first data storage node which electrically connects the first current electrode of the first transfer transistor, the first current electrode of the first latch transistor, the control electrode of the second latch transistor, the control electrode of the second vertical load transistor, and the first current electrode of the first vertical load transistor; a second data storage node which electrically connects the first current electrode of the second transfer transistor, the first current electrode of the second latch transistor, the control electrode of the first latch transistor, the control electrode of the first vertical load transistor, and the first current electrode of the second vertical load transistor; and first interconnect means which at least partially underlies the control electrode of the second latch transistor and which electrically connects the control electrode of the second latch transistor to the first current electrode of the first transfer transistor.
Claim 2
Dependent Claim
258 words
An integrated circuit memory device having a plurality of cells, each cell comprising: first and second latch transistors, each latch transistor having a control electrode and first and second current electrodes; first and second transfer transistors, each transfer transistor having a control electrode and first and second current electrodes; first and second vertical load transistors, each load transistor being positioned within a substantially vertical wall trench and having a first current electrode located adjacent a bottom surface of the trench, a second current electrode, a channel region along the substantially vertical wall of the trench which connects the first and second current electrodes, and a control electrode contained within the trench; a first data storage node which electrically connects the first current electrode of the first transfer transistor, the first current electrode of the first latch transistor, the control electrode of the second latch transistor, the control electrode of the second vertical load transistor, and the first current electrode of the first vertical load transistor; a second data storage node which electrically connects the first current electrode of the second transfer transistor, the first current electrode of the second latch transistor, the control electrode of the first latch transistor, the control electrode of the first vertical load transistor, and the first current electrode of the second vertical load transistor; and first interconnect means which at least partially underlies the control electrode of the second latch transistor and which electrically connects the control electrode of the second latch transistor to the first current electrode of the first transfer transistor.
Claim 3
Dependent Claim
29 words
The memory device of claim 1 wherein the first and second current electrodes and the channel regions of the first and second vertical load transistors are comprised of polysilicon.
Claim 4
Dependent Claim
48 words
The memory device of claim 1 further comprising second interconnect means which at least partially underlies the control electrode of the first vertical load transistor and which electrically connects the first current electrode of the first vertical load transistor to the control electrode of the second latch transistor.
Claim 5
Dependent Claim
16 words
The memory device of claim 3 wherein the second interconnect means comprises a conductive landing pad.
Claim 6
Dependent Claim
15 words
The memory device of claim 4 wherein the conductive landing pad is comprised of polysilicon.
Claim 7
Dependent Claim
15 words
The memory device of claim 1 wherein the first interconnect means is a buried contact.
Claim 8
Dependent Claim
16 words
The memory device of claim 1 wherein the first interconnect means is a strapped local interconnect.
Claim 9
Dependent Claim
163 words
A structural layout for an integrated circuit memory device having an array of memory cells, at least one cell having a plurality of transistors and at least one data storage node, a minimum feature, and an enclosed area defined by a perimeter of the minimum feature, the enclosed area of the layout comprising: an active region which functions as a current electrode of a first transistor; first interconnect means within a portion of the active region; a first conductive material forming a control electrode of a second transistor and overlapping a portion of the first interconnect means to electrically couple the control electrode of the second transistor to the active region; second interconnect means overlapping a portion of the first conductive material; a second conductive material overlapping the second interconnect means, the second conductive material functioning as current electrodes of a third transistor; and a third conductive material forming a control electrode of the third transistor and contained within the second interconnect means.
Claim 10
Dependent Claim
163 words
A structural layout for an integrated circuit memory device having an array of memory cells, at least one cell having a plurality of transistors and at least one data storage node, a minimum feature, and an enclosed area defined by a perimeter of the minimum feature, the enclosed area of the layout comprising: an active region which functions as a current electrode of a first transistor; first interconnect means within a portion of the active region; a first conductive material forming a control electrode of a second transistor and overlapping a portion of the first interconnect means to electrically couple the control electrode of the second transistor to the active region; second interconnect means overlapping a portion of the first conductive material; a second conductive material overlapping the second interconnect means, the second conductive material functioning as current electrodes of a third transistor; and a third conductive material forming a control electrode of the third transistor and contained within the second interconnect means.
Claim 11
Dependent Claim
55 words
The structural layout of claim 8 wherein the enclosed area further comprises: third interconnect means overlapping a portion of the control electrode of the second transistor; and a fourth conductive material overlapping the third interconnect means to electrically couple the fourth conductive material, the second conductive material, and the control electrode of the second transistor.
Claim 12
Dependent Claim
25 words
The structural layout of claim 9 wherein the first conductive material, second conductive material, third conductive material, and fourth conductive material are comprised of polysilicon.
Claim 13
Dependent Claim
36 words
The structural layout of claim 8 wherein the first transistor functions as a transfer transistor, the second transistor functions as a latch transistor, and the third transistor functions as a load transistor in an SRAM cell.
Claim 14
Dependent Claim
19 words
The structural layout of claim 8 wherein the first interconnect means is a buried contact formed in a substrate.
Claim 15
Dependent Claim
16 words
The structural layout of claim 8 wherein the first interconnect means is a strapped local interconnect.
Claim 16
Dependent Claim
266 words
A structural layout for an integrated circuit memory device having an array of memory cells, at least one cell having a plurality of transistors and first and second data storage nodes, each data storage node having a minimum feature and an enclosed area defined by a perimeter of the minimum feature, the enclosed area of the first data storage node of the layout comprising: an active region which functions as a current electrode of a first transistor; first interconnect means within a portion of the active region; a first conductive material forming a control electrode of a second transistor and overlapping a portion of the first interconnect means to electrically couple the control electrode of the second transistor to the active region; second interconnect means overlapping a portion of the control electrode of the second transistor; a second conductive material overlapping the second interconnect means to electrically couple the second conductive material to the control electrode of the second transistor; third interconnect means overlapping a portion of the second conductive material; a third conductive material overlapping the third interconnect means to electrically couple the third conductive material to the second conductive material, the third conductive material functioning as current electrodes of a third transistor; and a fourth conductive material forming a control electrode of the third transistor and contained within the third interconnect means; and a fourth interconnect means located outside the enclosed area of the first data storage node but contained within the at least one cell, the fourth interconnect means connecting the control electrode of the third transistor to the second data storage node.
Claim 17
Dependent Claim
266 words
A structural layout for an integrated circuit memory device having an array of memory cells, at least one cell having a plurality of transistors and first and second data storage nodes, each data storage node having a minimum feature and an enclosed area defined by a perimeter of the minimum feature, the enclosed area of the first data storage node of the layout comprising: an active region which functions as a current electrode of a first transistor; first interconnect means within a portion of the active region; a first conductive material forming a control electrode of a second transistor and overlapping a portion of the first interconnect means to electrically couple the control electrode of the second transistor to the active region; second interconnect means overlapping a portion of the control electrode of the second transistor; a second conductive material overlapping the second interconnect means to electrically couple the second conductive material to the control electrode of the second transistor; third interconnect means overlapping a portion of the second conductive material; a third conductive material overlapping the third interconnect means to electrically couple the third conductive material to the second conductive material, the third conductive material functioning as current electrodes of a third transistor; and a fourth conductive material forming a control electrode of the third transistor and contained within the third interconnect means; and a fourth interconnect means located outside the enclosed area of the first data storage node but contained within the at least one cell, the fourth interconnect means connecting the control electrode of the third transistor to the second data storage node.
Claim 18
Dependent Claim
62 words
The structural layout of claim 14 wherein the enclosed area of the second data storage node has a layout substantially identical to the enclosed area of the first data storage node, a second conductive material of the second data storage node being coupled to the control electrode of the third transistor of the first data storage node by the fourth interconnect means.
Claim 19
Dependent Claim
25 words
The structural layout of claim 15 wherein the first conductive material, second conductive material, third conductive material, and fourth conductive material are comprised of polysilicon.
Claim 20
Dependent Claim
36 words
The structural layout of claim 15 wherein the first transistor functions as a transfer transistor, the second transistor functions as a latch transistor, and the third transistor functions as a load transistor in an SRAM cell.
Claim 21
Dependent Claim
16 words
The structural layout of claim 17 wherein the third transistor is a vertically oriented thin-film transistor.
Claim 22
Dependent Claim
19 words
The structural layout of claim 15 wherein the third interconnect means is a trench formed in a dielectric material.
Claim 23
Dependent Claim
20 words
The structural layout of claim 15 wherein the third conductive material also functions as V cc of the memory device.
Claim 24
Dependent Claim
19 words
The structural layout of claim 8 wherein the second interconnect means is a trench formed in a dielectric material.
Claim 25
Dependent Claim
19 words
The structural layout of claim 8 wherein the second interconnect means is a through-hole formed in a dielectric material.
Claim 26
Dependent Claim
16 words
The structural layout of claim 8 wherein the third transistor is a vertically oriented thin-film transistor.
Claim 27
Dependent Claim
22 words
The structural layout of claim 8 wherein the third conductive material also functions as V cc of the integrated circuit memory device.
Claim 28
Dependent Claim
19 words
The structural layout of claim 15 wherein the first interconnect means is a buried contact formed in a substrate.
References Cited (Backward Citations)
US5016070A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-29 | 1996-09-28 | 1997-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-29 | 2000-09-28 | 2001-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-29 | 2004-09-28 | 2005-03-30 | $7700.00 | Window Closed / Lapsed |