Patent US5807660A successfully refreshed from Google Patents.
US5807660A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Avoid photoresist lifting by post-oxide-dep plasma treatment
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-02-03
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Granted: 1998-09-15
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Expires: 2017-02-03
Abstract
Abstract A new method to improve the adhesion of a photoresist layer to an underlying dielectric layer in the fabrication of integrated circuit devices is described. Semiconductor device structures are provided in and on a semiconductor substrate. A dielectric layer is deposited over the semiconductor device structures wherein the depositing is performed in a deposition chamber. The dielectric layer is treated with a N 2 O plasma treatment while the substrate is still within the deposition chamber. The substrate is removed from the deposition chamber. A photoresist mask is formed over the dielectric layer with an opening above the semiconductor device structures to be electrically contacted wherein the plasma treatment improves adhesion of the photoresist mask to the dielectric layer when compared to a conventional integrated circuit device. A contact opening is etched through the dielectric layer not covered by the mask to the semiconductor device structures to be electrically contacted. A conducting material is deposited within the contact opening completing the electrical contact in the fabrication of the integrated circuit device.
Inventors
- 👤 Kuang-Hung Lin
- 👤 Dong-Hsu Cheng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:29
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; G; G03; G03F; G03F7/00; G03F7/16; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/65; H10P14/6516; H10P14/6529; H10P14/6532; H10P14/6922; H10P14/6923; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10W20/093; H10W20/096; G03F7/004; G03F7/085
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
180 words
A method for making an electrical contact in the fabrication of an integrated circuit device comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a dielectric layer over said semiconductor device structures wherein said depositing is performed in a deposition chamber and wherein at least the top portion of said dielectric layer comprises silicon oxide; treating said dielectric layer with a plasma treatment selected from the group containing N 2 O, N 2 , and Ar while said substrate is still within said deposition chamber; removing said substrate from said deposition chamber; forming a photoresist mask over said dielectric layer with an opening above said semiconductor device structures to be electrically contacted wherein said plasma treatment improves adhesion of said photoresist mask to said dielectric layer when compared to a conventional integrated circuit device; etching a contact opening through said dielectric layer not covered by said mask to said semiconductor device structures to be electrically contacted; and depositing a conducting material within said contact opening completing said electrical contact in the fabrication of said integrated circuit device.
Claim 2
Independent Claim
180 words
A method for making an electrical contact in the fabrication of an integrated circuit device comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a dielectric layer over said semiconductor device structures wherein said depositing is performed in a deposition chamber and wherein at least the top portion of said dielectric layer comprises silicon oxide; treating said dielectric layer with a plasma treatment selected from the group containing N 2 O, N 2 , and Ar while said substrate is still within said deposition chamber; removing said substrate from said deposition chamber; forming a photoresist mask over said dielectric layer with an opening above said semiconductor device structures to be electrically contacted wherein said plasma treatment improves adhesion of said photoresist mask to said dielectric layer when compared to a conventional integrated circuit device; etching a contact opening through said dielectric layer not covered by said mask to said semiconductor device structures to be electrically contacted; and depositing a conducting material within said contact opening completing said electrical contact in the fabrication of said integrated circuit device.
Claim 3
Dependent Claim
24 words
The method according to claim 1 wherein said semiconductor device structures to be electrically contacted are source/drain regions of a CMOS integrated circuit device.
Claim 4
Dependent Claim
31 words
The method according to claim 1 wherein said semiconductor device structures are a metallurgy layer and said electrical contact is a via metallurgy between metal layers in said integrated circuit device.
Claim 5
Dependent Claim
26 words
The method according to claim 1 wherein said dielectric layer structure is composed of silicon oxide doped with one of the group including boron and phosphorus.
Claim 6
Dependent Claim
17 words
The method according to claim 1 wherein said dielectric layer structure is composed of undoped silicon oxide.
Claim 7
Dependent Claim
43 words
The method according to claim 1 wherein the conditions within said deposition chamber are a temperature of between about 200° and 500° C., a pressure of between about 2 and 10 torr, and a radio frequency of between about 100 and 500 watts.
Claim 8
Dependent Claim
36 words
The method according to claim 1 wherein said plasma treatment comprises flowing N 2 O plasma at the rate of between about 500 and 2000 sccm for a duration of between about 5 and 60 seconds.
Claim 9
Dependent Claim
35 words
The method according to claim 1 wherein said plasma treatment comprises flowing N 2 plasma at the rate of between about 500 and 2000 sccm for a duration of between about 5 and 60 seconds.
Claim 10
Dependent Claim
34 words
The method according to claim 1 wherein said plasma treatment comprises flowing Ar plasma at the rate of between about 500 and 2000 sccm for a duration of between about 5 and 60 seconds.
Claim 11
Dependent Claim
16 words
The method according to claim 1 further comprising depositing a glue layer underlying said conducting layer.
Claim 12
Dependent Claim
23 words
The method according to claim 10 wherein said glue layer comprises a first layer of titanium nitride and a second layer of titanium.
Claim 13
Dependent Claim
22 words
The method according to claim 1 wherein said etching comprises a first isotropic wet etch followed by a second anisotropic dry etch.
Claim 14
Dependent Claim
13 words
The method according to claim 1 wherein said conducting layer comprises a metal.
Claim 15
Independent Claim
171 words
A method for making an electrical contact in the fabrication of an integrated circuit device comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a silicon oxide layer over said semiconductor device structures wherein said depositing is performed in a deposition chamber; treating said silicon oxide layer with a plasma treatment selected from the group containing N 2 O, N 2 , and Ar while said substrate is still within said deposition chamber; removing said substrate from said deposition chamber; forming a photoresist mask over said silicon oxide layer with an opening above said semiconductor device structures to be electrically contacted wherein said plasma treatment improves adhesion of said photoresist mask to said silicon oxide layer when compared to a conventional integrated circuit device; etching a contact opening through said silicon oxide layer not covered by said mask to said semiconductor device structures to be electrically contacted; and depositing a conducting material within said contact opening completing said electrical contact in the fabrication of said integrated circuit device.
Claim 16
Independent Claim
171 words
A method for making an electrical contact in the fabrication of an integrated circuit device comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a silicon oxide layer over said semiconductor device structures wherein said depositing is performed in a deposition chamber; treating said silicon oxide layer with a plasma treatment selected from the group containing N 2 O, N 2 , and Ar while said substrate is still within said deposition chamber; removing said substrate from said deposition chamber; forming a photoresist mask over said silicon oxide layer with an opening above said semiconductor device structures to be electrically contacted wherein said plasma treatment improves adhesion of said photoresist mask to said silicon oxide layer when compared to a conventional integrated circuit device; etching a contact opening through said silicon oxide layer not covered by said mask to said semiconductor device structures to be electrically contacted; and depositing a conducting material within said contact opening completing said electrical contact in the fabrication of said integrated circuit device.
Claim 17
Dependent Claim
24 words
The method according to claim 14 wherein said semiconductor device structures to be electrically contacted are source/drain regions of a CMOS integrated circuit device.
Claim 18
Dependent Claim
31 words
The method according to claim 14 wherein said semiconductor device structures are a metallurgy layer and said electrical contact is a via metallurgy between metal layers in said integrated circuit device.
Claim 19
Dependent Claim
22 words
The method according to claim 14 wherein said silicon oxide layer is doped with one of the group including boron and phosphorus.
Claim 20
Dependent Claim
13 words
The method according to claim 14 wherein said silicon oxide layer is undoped.
Claim 21
Dependent Claim
43 words
The method according to claim 14 wherein the conditions within said deposition chamber are a temperature of between about 200° and 500° C., a pressure of between about 2 and 10 torr, and a radio frequency of between about 100 to 500 watts.
Claim 22
Dependent Claim
31 words
The method according to claim 14 wherein said plasma is flowed at the rate of between about 500 and 2000 sccm for a duration of between about 5 and 60 seconds.
Claim 23
Independent Claim
214 words
A method for making an electrical contact in the fabrication of an integrated circuit device wherein photoresist adhesion is improved in the inventive integrated circuit device when compared to photoresist adhesion in a conventional integrated circuit device comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a silicon oxide dielectric layer over said semiconductor device structures wherein said depositing is performed in a deposition chamber; treating said dielectric layer with a plasma treatment whereby the surface of said dielectric layer is roughened wherein said plasma comprises one of the group containing N 2 O, N 2 , and Ar while said substrate is still within said deposition chamber; removing said substrate from said deposition chamber; forming a photoresist mask over said dielectric layer with an opening above said semiconductor device structures to be electrically contacted wherein said roughened surface of said dielectric layer allows for better photoresist adhesion of said photoresist mask to said dielectric layer when compared to said photoresist adhesion in said conventional integrated circuit device; etching a contact opening through said dielectric layer not covered by said mask to said semiconductor device structures to be electrically contacted; and depositing a conducting material within said contact opening completing said electrical contact in the fabrication of said integrated circuit device.
Claim 24
Independent Claim
214 words
A method for making an electrical contact in the fabrication of an integrated circuit device wherein photoresist adhesion is improved in the inventive integrated circuit device when compared to photoresist adhesion in a conventional integrated circuit device comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a silicon oxide dielectric layer over said semiconductor device structures wherein said depositing is performed in a deposition chamber; treating said dielectric layer with a plasma treatment whereby the surface of said dielectric layer is roughened wherein said plasma comprises one of the group containing N 2 O, N 2 , and Ar while said substrate is still within said deposition chamber; removing said substrate from said deposition chamber; forming a photoresist mask over said dielectric layer with an opening above said semiconductor device structures to be electrically contacted wherein said roughened surface of said dielectric layer allows for better photoresist adhesion of said photoresist mask to said dielectric layer when compared to said photoresist adhesion in said conventional integrated circuit device; etching a contact opening through said dielectric layer not covered by said mask to said semiconductor device structures to be electrically contacted; and depositing a conducting material within said contact opening completing said electrical contact in the fabrication of said integrated circuit device.
Claim 25
Dependent Claim
24 words
The method according to claim 21 wherein said semiconductor device structures to be electrically contacted are source/drain regions of a CMOS integrated circuit device.
Claim 26
Dependent Claim
31 words
The method according to claim 21 wherein said semiconductor device structures are a metallurgy layer and said electrical contact is a via metallurgy between metal layers in said integrated circuit device.
Claim 27
Dependent Claim
65 words
The method according to claim 21 wherein said plasma treatment conditions comprise flowing said plasma at the rate of between about 500 and 2000 sccm for a duration of between about 5 and 60 seconds at a temperature of between about 200° and 500° C., a pressure of between about 2 and 10 torr, and a radio frequency of between about 100 and 500 watts.
Claim 28
Dependent Claim
39 words
The method according to claim 24 wherein said etching comprises a first isotropic wet etch followed by a second anisotropic dry etch and wherein the profile of said contact opening can be manipulated by changing said plasma treatment conditions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |