Furnace amorphous-SI cap layer to prevent tungsten volcano effect

Claim 1

The method of forming tungsten plug metallization without peeling of the tungsten or the glue layer in the fabrication of integrated circuits comprising: providing semiconductor device structures in and on a semiconductor substrate; providing an insulating layer covering said semiconductor device structures wherein a contact hole has been opened through said insulating layer to said semiconductor substrate; depositing a glue layer conformally over the surface of said insulating layer and within said contact opening; annealing said glue layer to prevent peeling of said glue layer; depositing a layer of amorphous silicon to a thickness of between about 50 to 100 Angstroms overlying said glue layer to prevent peeling of said glue layer and to prevent peeling of said tungsten to be deposited subsequently; and forming a tungsten plug within said contact opening in the fabrication of said integrated circuit.

Claim 2

The method of forming tungsten plug metallization without peeling of the tungsten or the glue layer in the fabrication of integrated circuits comprising: providing semiconductor device structures in and on a semiconductor substrate; providing an insulating layer covering said semiconductor device structures wherein a contact hole has been opened through said insulating layer to said semiconductor substrate; depositing a glue layer conformally over the surface of said insulating layer and within said contact opening; annealing said glue layer to prevent peeling of said glue layer; depositing a layer of amorphous silicon to a thickness of between about 50 to 100 Angstroms overlying said glue layer to prevent peeling of said glue layer and to prevent peeling of said tungsten to be deposited subsequently; and forming a tungsten plug within said contact opening in the fabrication of said integrated circuit.

Claim 9

The method of forming tungsten plug metallization without peeling of the tungsten or the glue layer in the fabrication of integrated circuits comprising: providing semiconductor device structures in and on a semiconductor substrate; providing an insulating layer covering said semiconductor device structures wherein a contact hole has been opened through said insulating layer to said semiconductor substrate; depositing a layer of titanium conformally over the surface of said insulating layer and within said contact opening; depositing a layer of titanium nitride over said titanium layer; annealing said titanium nitride layer in a nitrogen ambient at a temperature of between about 400° to 480° C. wherein nitrogen atoms from said nitrogen ambient fill the grain boundaries of said titanium nitride layer preventing penetration of said titanium nitride layer by subsequent metallization and wherein said preventing penetration prevents peeling of said titanium nitride layer; depositing a layer of amorphous silicon to a thickness of between about 50 to 100 Angstroms overlying said titanium nitride layer to prevent peeling of said titanium nitride layer and to prevent peeling of said tungsten to be deposited subsequently; and forming a tungsten plug within said contact opening in the fabrication of said integrated circuit.

Claim 10

The method of forming tungsten plug metallization without peeling of the tungsten or the glue layer in the fabrication of integrated circuits comprising: providing semiconductor device structures in and on a semiconductor substrate; providing an insulating layer covering said semiconductor device structures wherein a contact hole has been opened through said insulating layer to said semiconductor substrate; depositing a layer of titanium conformally over the surface of said insulating layer and within said contact opening; depositing a layer of titanium nitride over said titanium layer; annealing said titanium nitride layer in a nitrogen ambient at a temperature of between about 400° to 480° C. wherein nitrogen atoms from said nitrogen ambient fill the grain boundaries of said titanium nitride layer preventing penetration of said titanium nitride layer by subsequent metallization and wherein said preventing penetration prevents peeling of said titanium nitride layer; depositing a layer of amorphous silicon to a thickness of between about 50 to 100 Angstroms overlying said titanium nitride layer to prevent peeling of said titanium nitride layer and to prevent peeling of said tungsten to be deposited subsequently; and forming a tungsten plug within said contact opening in the fabrication of said integrated circuit.

Claim 16

The method of forming tungsten plug metallization without peeling of the tungsten or the glue layer in the fabrication of integrated circuits comprising: providing semiconductor device structures in and on a semiconductor substrate; providing an insulating layer covering said semiconductor device structures wherein a contact hole has been opened through said insulating layer to said semiconductor substrate; depositing a glue layer conformally over the surface of said insulating layer and within said contact opening; annealing said glue layer in a nitrogen ambient at a temperature of between about 580° to 650° C. wherein nitrogen atoms from said nitrogen ambient fill the grain boundaries of said glue layer preventing penetration of said glue layer by subsequent metallization and wherein said preventing penetration prevents peeling of said glue layer; depositing a layer of amorphous silicon overlying said glue layer wherein said amorphous silicon layer will prevent penetration of said underlying glue layer by subsequent metallization and wherein said preventing penetration prevents said peeling of said glue layer and prevents peeling of said tungsten to be deposited subsequently; and forming a tungsten plug within said contact opening in the fabrication of said integrated circuit.

Claim 17

The method of forming tungsten plug metallization without peeling of the tungsten or the glue layer in the fabrication of integrated circuits comprising: providing semiconductor device structures in and on a semiconductor substrate; providing an insulating layer covering said semiconductor device structures wherein a contact hole has been opened through said insulating layer to said semiconductor substrate; depositing a glue layer conformally over the surface of said insulating layer and within said contact opening; annealing said glue layer in a nitrogen ambient at a temperature of between about 580° to 650° C. wherein nitrogen atoms from said nitrogen ambient fill the grain boundaries of said glue layer preventing penetration of said glue layer by subsequent metallization and wherein said preventing penetration prevents peeling of said glue layer; depositing a layer of amorphous silicon overlying said glue layer wherein said amorphous silicon layer will prevent penetration of said underlying glue layer by subsequent metallization and wherein said preventing penetration prevents said peeling of said glue layer and prevents peeling of said tungsten to be deposited subsequently; and forming a tungsten plug within said contact opening in the fabrication of said integrated circuit.