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Process for manufacturing a packaged semiconductor having a divided leadframe stage

Assignee: Kyushu Fujitsu Electronics Ltd
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Filing: 1995-11-21
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Granted: 1998-09-08
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Expires: 2015-11-21
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Abstract

Abstract A process for manufacturing semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.

Inventors

  • 👤 Kazuto Tsuji
  • 👤 Yoshiyuki Yoneda
  • 👤 Hideharu Sakoda
  • 👤 Michio Sono
  • 👤 Ichiro Yamaguchi
  • 👤 Toshio Hamano
  • 👤 Yoshihiro Kubota
  • 👤 Michio Hayakawa
  • 👤 Yoshihiko Ikemoto
  • 👤 Yukio Saigo
  • 👤 Naomi Miyaji

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 20:13
CPC Classifications
H; H10; H10W; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H10W40/00; H10W40/70; H10W40/77; H10W40/778; H10W70/00; H10W70/40; H10W70/421; H10W70/424; H10W70/456; H10W70/457; H10W72/00; H10W72/30; H10W72/50; H10W76/60; H10W70/60; H10W70/67; H10W70/68; H10W70/682; H10W70/685; H10W72/071; H10W72/073; H10W72/07331; H10W72/07336; H10W72/075; H10W72/07551; H10W72/07554; H10W72/321; H10W72/325; H10W72/351; H10W72/352; H10W72/541; H10W72/5449; H10W72/547; H10W72/5473; H10W72/551; H10W72/552; H10W72/5524; H10W72/851; H10W72/874; H10W72/884; H10W74/00; H10W74/10; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 101 words
A method of producing a semiconductor device, comprising the steps of: (a) mounting a semiconductor chip on a first surface of a stage of a lead frame, said first surface having grooves formed thereupon, said grooves dividing the stage into a plurality of areas, (b) establishing electrical connections between the semiconductor chip, the stage and the leads; (c) forming a package which seals the semiconductor chip; (d) removing a surface of the package so that a second surface of the stage, opposite to the first surface, appears so that the plurality of areas of the stage are separated from each other.
Claim 2
Independent Claim 101 words
A method of producing a semiconductor device, comprising the steps of: (a) mounting a semiconductor chip on a first surface of a stage of a lead frame, said first surface having grooves formed thereupon, said grooves dividing the stage into a plurality of areas, (b) establishing electrical connections between the semiconductor chip, the stage and the leads; (c) forming a package which seals the semiconductor chip; (d) removing a surface of the package so that a second surface of the stage, opposite to the first surface, appears so that the plurality of areas of the stage are separated from each other.
Claim 3
Dependent Claim 24 words
The method as claimed in claim 1, further comprising the step (e) of plating outer lead portions of the leads with a metallic film.
Claim 4
Dependent Claim 23 words
The method as claimed in claim 1, further comprising the step (e) of forming bump electrodes on the second surface of the stage.
Claim 5
Dependent Claim 25 words
The method as claimed in claim 1, further comprising the step (e) of attaching a heat radiating member to the second surface of the stage.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-09-07 2002-03-09 2002-09-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-09-07 2006-03-09 2006-09-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-09-07 2010-03-09 2010-09-08 $7700.00 Window Closed / Lapsed

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