Patent US5802070A successfully refreshed from Google Patents.
US5802070A
Expired / Lapsed
US
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Testing associative memory
Assignee: International Business Machines Corp
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Filing: 1996-10-03
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Granted: 1998-09-01
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Expires: 2016-10-03
Abstract
Abstract A method of testing a first memory such as a RAM having data storage at a plurality of individually addressable storage locations is provided. A portion of the address for the addressable locations of the first memory is supplied as an output from a second memory such as a CAM. The second memory includes a decoder to provide a decoded address as input signals to the second memory. During the testing, first memory specific addresses are provided to the decoder as input. These first memory specific addresses are decoded by the decoder and are gated as input signals to address the first memory. In this way, the decoder which in normal operation provides decoded input signals to the CAM is used to provide input signals to the RAM, thus obviating the need for any scan chain latches surrounding the RAM. This enables conventional testing apparatus to provide the necessary test protocol for the RAM through the decoder normally used by the CAM.
Inventors
- 👤 Robert Dean Adams
- 👤 Kevin Arthur Batson
- 👤 George Maria Braceras
- 👤 Fred John Towler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:52
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/48
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
163 words
A method of testing a first memory having a data storage at a plurality of individually addressable storage locations, each location having an individual address, and at least a portion of the individual addresses for the storage locations to be accessed during a normal read/write cycle being supplied as an output from a second memory, and wherein said second memory has a decoder associated therewith to provide decoded addresses as input signals to said second memory, comprising the steps of: during a testing cycle: providing first memory specific addresses as inputs to said decoder; decoding each said first memory specific address in said decoder; and providing the output of said decoder as input signals representing/as said at least a portion of the individual addresses to be accessed to said first memory; wherein said step of providing the output of said decoder comprising using said decoder to generate input signals directly, not through the second memory to said first memory during the testing cycle.
Claim 2
Independent Claim
163 words
A method of testing a first memory having a data storage at a plurality of individually addressable storage locations, each location having an individual address, and at least a portion of the individual addresses for the storage locations to be accessed during a normal read/write cycle being supplied as an output from a second memory, and wherein said second memory has a decoder associated therewith to provide decoded addresses as input signals to said second memory, comprising the steps of: during a testing cycle: providing first memory specific addresses as inputs to said decoder; decoding each said first memory specific address in said decoder; and providing the output of said decoder as input signals representing/as said at least a portion of the individual addresses to be accessed to said first memory; wherein said step of providing the output of said decoder comprising using said decoder to generate input signals directly, not through the second memory to said first memory during the testing cycle.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein said first memory is a RAM and said second memory is a CAM.
Claim 4
Dependent Claim
22 words
The method of claim 1 wherein said first memory specific address is a read address to be accessed during a read cycle.
Claim 5
Dependent Claim
19 words
The method of claim 1 wherein said testing is performed on both a read cycle and a write cycle.
Claim 6
Independent Claim
229 words
An apparatus for testing a first memory having a data storage at a plurality of individually addressable storage locations, each location having an individual address, and at least a portion of the individual addresses for the storage locations to be accessed during a normal read/write cycle being supplied as an output from a second memory, and wherein said second memory has a decoder associated therewith to provide decoded addresses as input signals to said second memory comprising: first circuitry to selectively provide first memory and second memory specific addresses as inputs to said decoder; second circuitry to selectively provide the outputs of said decoder as input signals representing said at least a portion of the individual addresses to be accessed directly, not through the second memory to said first memory when said addresses are first memory specific during a testing cycle and to selectively provide the outputs of said decoder as input signals representing said at least a portion of the individual addresses to be accessed through said second memory to said first memory when said addresses are second memory specific during a normal read/write cycle; wherein said second circuit includes logic associated with said decoder for generating input signals to said first memory during a testing cycle and input signals directly, not through the second memory to said first memory through said second memory during normal read/write cycles.
Claim 7
Independent Claim
229 words
An apparatus for testing a first memory having a data storage at a plurality of individually addressable storage locations, each location having an individual address, and at least a portion of the individual addresses for the storage locations to be accessed during a normal read/write cycle being supplied as an output from a second memory, and wherein said second memory has a decoder associated therewith to provide decoded addresses as input signals to said second memory comprising: first circuitry to selectively provide first memory and second memory specific addresses as inputs to said decoder; second circuitry to selectively provide the outputs of said decoder as input signals representing said at least a portion of the individual addresses to be accessed directly, not through the second memory to said first memory when said addresses are first memory specific during a testing cycle and to selectively provide the outputs of said decoder as input signals representing said at least a portion of the individual addresses to be accessed through said second memory to said first memory when said addresses are second memory specific during a normal read/write cycle; wherein said second circuit includes logic associated with said decoder for generating input signals to said first memory during a testing cycle and input signals directly, not through the second memory to said first memory through said second memory during normal read/write cycles.
Claim 8
Dependent Claim
19 words
The device of claim 5 wherein said first memory is a RAM and said second memory is a CAM.
Claim 9
Dependent Claim
18 words
The device of claim 5 wherein said circuitry to select the output of said decoder includes logic gates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |