Bit map addressing schemes for flash memory

Claim 1

A memory device comprising: an output; a plurality of address inputs including row address inputs, column address inputs, and at least one multi-level cell (MLC) address input; a memory cell array arranged in a plurality of rows and columns, the memory cell array comprising a plurality of memory cells wherein each memory cell is operative to store n bits of data, wherein n is greater than 1, each of the n bits of a memory cell having a different address; a row decoder circuit coupled to the memory cell array wherein the row decoder circuit selects a row of the memory cell array in response to a row address received via the row address inputs; a column decoder circuit coupled to the memory cell array wherein the column decoder circuit selects a column of the memory cell array in response to a column address received via the column address inputs such that a first memory cell is selected for reading in response to the row and column addresses; a sensing circuit coupled to the first memory cell and the output, the sensing circuit for determining a state for each of the n bits stored in the first memory cell; and a selecting circuit coupled to the sensing circuit, the MLC address input, and to the output, the selecting circuit for addressing and providing only one of the n bits from the sensing circuit to the output in response to the MLC address input such that each of the n bits stored by the first memory cell is individually addressed and output.