Semiconductor memory device including redundant memory cell array for repairing defect

Claim 2

A semiconductor memory device, comprising: a plurality of memory cell array groups each including at least one memory cell array, said memory cell array including memory cells arranged in rows and columns; a single redundant memory cell array block provided in common for all of said memory cell arrays, for replacing an arbitrary defect column in all the memory cell arrays included in said plurality of memory cell array groups, said redundant memory cell array block including redundant memory cells arranged in rows and columns; defect address storage means for storing a defect address signal indicating a defective portion in said memory cell array; address coincidence detecting means for detecting a coincidence of an externally applied address signal and the defect address signal stored in said defect address storage means; redundant access means responsive to said address coincidence detecting means for accessing said redundant memory cell array block in place of said memory cell array including said defective portion; test mode detecting means for detecting a designation of an external test mode; and coincidence/non-coincidence detecting means responsive to test mode detecting means for reading data from a memory cell array in said plurality of memory cell array groups to detect a coincidence/non-coincidence of the read data, wherein, when a defect column exists in a memory cell array included in any of said plurality of memory cell groups, said coincidence/non-coincidence detecting means reads data from a corresponding column to be replaced in said redundant memory cell array, instead of reading data from the defect column in the group including the defect column.

Claim 3

The semiconductor memory device according to claim 1, wherein said defect address storage means includes a plurality of defect address programming means for programming a plurality of defect address signals indicating a plurality of defective portions in a memory cell array included in said plurality of memory cell array groups, and said address coincidence detecting means includes a plurality of programmed address coincidence detecting means for detecting a coincidence of said externally applied address signal and an address signal programmed in said plurality of defect address programming means.

Claim 4

The semiconductor memory device according to claim 2, wherein said redundant memory cell array block includes a plurality of redundant memory cell areas, each corresponding to one of said plurality of programmed address coincidence detecting means, and said redundant access means accesses a corresponding one of said plurality of redundant memory cell areas in response to a corresponding one of said plurality of programmed address coincidence detecting means.

Claim 5

The semiconductor memory device according to claim 1, wherein said redundant access means includes data selecting means for providing data read from said redundant memory cell array block in place of data read from said plurality of memory cell arrays, in response to said address coincidence detecting means.

Claim 6

The semiconductor memory device according to claim 4, wherein said redundant access means further includes row selecting means responsive to an externally applied row address signal for selecting a row to be accessed in said redundant memory cell array, and column selecting means responsive to said address coincidence detecting means for selecting a column to be accessed in said redundant memory cell array.

Claim 7

The semiconductor memory device according to claim 4, wherein said redundant access means further includes sense amplifier means coupled between said redundant memory cell array block and said data selecting means for amplifying data read from said redundant memory cell array.

Claim 8

The semiconductor memory device according to claim 3, wherein said plurality of redundant memory cell areas include a plurality of redundant memory cell columns provided in said redundant memory cell array block.

Claim 9

The semiconductor memory device according to claim 1, wherein said memory device includes a static random access memory.

Claim 10

A semiconductor memory device, comprising: a first memory cell array group including at least one memory cell array; a second memory cell array group including at least one memory cell array; each memory cell array included in said first and second memory cell array groups including memory cells arranged in rows and columns; a single redundant memory cell array block provided in common for said first and second memory cell array groups, for replacing an arbitrary defect column in all the memory cell arrays included in said first and second memory cell array groups, said redundant memory cell array block including redundant memory cells arranged in rows and columns; defect address storage means for storing a defect address signal indicating a defect column in said memory cell array; address coincidence defecting means for defecting a coincidence of an externally applied address signal and the defect address signal stored in said defect address storage means; redundant access means responsive to said address coincidence defecting means for accessing said redundant memory cell array block in place of said memory cell array including said defective column; test mode detecting means for detecting a designation of an external test mode; and coincidence/non-coincidence detecting means responsive to said test mode detecting means for detecting a coincidence/non-coincidence of data read from a memory cell array of said first memory cell array group and data read from a memory cell array of said second memory cell array group, wherein, when a defect column exists in a memory cell array included in either of said first and second memory cell array group, said coincidence/non-coincidence detecting means reads data from a corresponding column to be replaced in said redundant memory cell array, instead of reading data from the defect column in the memory cell array group including the defect column.

Claim 11

A semiconductor memory device, comprising: a first memory cell array group including at least one memory cell array; a second memory cell array group including at least one memory cell array; each memory cell array included in said first and second memory cell array groups including memory cells arranged in rows and columns; a single redundant memory cell array block provided in common for said first and second memory cell array groups, for replacing an arbitrary defect column in all the memory cell arrays included in said first and second memory cell array groups, said redundant memory cell array block including redundant memory cells arranged in rows and columns; defect address storage means for storing a defect address signal indicating a defect column in said memory cell array; address coincidence defecting means for defecting a coincidence of an externally applied address signal and the defect address signal stored in said defect address storage means; redundant access means responsive to said address coincidence defecting means for accessing said redundant memory cell array block in place of said memory cell array including said defective column; test mode detecting means for detecting a designation of an external test mode; and coincidence/non-coincidence detecting means responsive to said test mode detecting means for detecting a coincidence/non-coincidence of data read from a memory cell array of said first memory cell array group and data read from a memory cell array of said second memory cell array group, wherein, when a defect column exists in a memory cell array included in either of said first and second memory cell array group, said coincidence/non-coincidence detecting means reads data from a corresponding column to be replaced in said redundant memory cell array, instead of reading data from the defect column in the memory cell array group including the defect column.

Claim 12

The semiconductor memory device according to claim 9, wherein, said defect address storage means includes a plurality of defect address programming means for programming a plurality of defect address signals indicating a plurality of defective portions in a memory cell array included in said first and second memory cell array groups, and said address coincidence detecting means includes a plurality of programmed address coincidence detecting means for detecting a coincidence of said externally applied address signal and an address signal programmed in said plurality of defect address programming means.

Claim 13

The semiconductor memory device according to claim 10, wherein said redundant memory cell array block includes a plurality of redundant memory cell areas, each corresponding to one of said plurality of programmed address coincidence detecting means, and said redundant access means accesses a corresponding one of said plurality of redundant memory cell areas in response to a corresponding one of said plurality of programmed address coincidence detecting means.

Claim 14

The semiconductor memory device according to claim 9, wherein said redundant access means includes data selecting means for providing data read from said redundant memory cell array block in place of data read from said plurality of memory cell arrays in response to said address coincidence detecting means.

Claim 15

The semiconductor memory device according to claim 12, wherein said redundant access means further includes row selecting means responsive to an externally applied row address signal for selecting a row to be accessed in said redundant memory cell array, and column selecting means responsive to said address coincidence detecting means for selecting a column to be accessed in said redundant memory cell array.

Claim 16

The semiconductor memory device according to claim 12, wherein said redundant access means further includes sense amplifier means coupled between said redundant memory cell array block and said data selecting means, for amplifying data read from said redundant memory cell array.

Claim 17

The semiconductor memory device according to claim 11, wherein said plurality of redundant memory cell areas include a plurality of redundant memory cell columns provided in said redundant memory cell array block.

Claim 18

The semiconductor memory device according to claim 9, wherein said memory device includes a static random access memory.

Claim 19

The semiconductor memory device according to claim 9, wherein said coincidence/non-coincidence detecting means includes first selecting means responsive to said address coincidence detecting means for selectively providing (i) multi-bit data read from said first memory cell array block, or (ii) multi-bit data including a plurality of bits except one bit corresponding to a defect column in the multi-bit data from said first block, and one bit from said redundant memory cell array block, second selecting means responsive to said address coincidence detecting means for selectively providing (i) multi-bit data read from said second memory cell array block, or (ii) multi-bit data including a plurality of bits except one bit corresponding to a defect column in the multi-bit data from said second block, and one bit from said redundant memory cell array block, and coincidence/non-coincidence detecting means for defecting a coincidence/non-coincidence of respective selected data from said first and second selecting means.

Claim 20

A semiconductor memory device, comprising: a plurality of memory cell array groups each including at least one memory cell array, said memory cell array including memory cells arranged in rows and columns; a plurality of data reading line groups provided correspondingly to said plurality of memory cell array groups, each group including a plurality of data reading lines for transferring multi-bit data from a memory cell array included in a corresponding memory cell array group; a single redundant memory cell array block provided in common for all of said memory cell arrays, for replacing an arbitrary defect column in all the memory cell arrays included in said plurality of memory cell array groups, said redundant memory cell array block including redundant memory cells arranged in rows and columns; a redundancy data reading line connected to said redundant memory cell array block for transferring one-bit data from the redundant memory cell array; defect address storage means for storing a defect address signal indicating a defective portion in said memory cell array; address coincidence detecting means for detecting a coincidence of an externally applied address signal and the defect address signal stored in said defect address storage means; redundant access means responsive to said address coincidence detecting means for accessing said redundant memory cell array in place of said memory cell array including said defective portion; test mode detecting means for detecting a designation of an external test mode; and coincidence/non-coincidence detecting means responsive to said test mode detecting means for reading multi-bit data through corresponding data reading lines from memory cell arrays in all of said memory cell array groups, respectively, to detect a coincidence/non-coincidence of the read data from respective memory cell array groups, when a defect column exists in a memory cell array included in any of said plurality of memory cell array groups, said coincidence/non-coincidence detecting means reading data from a corresponding column to be replaced in said redundant memory cell array through said redundancy reading line, instead of reading data from the defect column in the memory cell array group including the defect column.

Claim 21

A semiconductor memory device, comprising: a plurality of memory cell array groups each including at least one memory cell array, said memory cell array including memory cells arranged in rows and columns; a plurality of data reading line groups provided correspondingly to said plurality of memory cell array groups, each group including a plurality of data reading lines for transferring multi-bit data from a memory cell array included in a corresponding memory cell array group; a single redundant memory cell array block provided in common for all of said memory cell arrays, for replacing an arbitrary defect column in all the memory cell arrays included in said plurality of memory cell array groups, said redundant memory cell array block including redundant memory cells arranged in rows and columns; a redundancy data reading line connected to said redundant memory cell array block for transferring one-bit data from the redundant memory cell array; defect address storage means for storing a defect address signal indicating a defective portion in said memory cell array; address coincidence detecting means for detecting a coincidence of an externally applied address signal and the defect address signal stored in said defect address storage means; redundant access means responsive to said address coincidence detecting means for accessing said redundant memory cell array in place of said memory cell array including said defective portion; test mode detecting means for detecting a designation of an external test mode; and coincidence/non-coincidence detecting means responsive to said test mode detecting means for reading multi-bit data through corresponding data reading lines from memory cell arrays in all of said memory cell array groups, respectively, to detect a coincidence/non-coincidence of the read data from respective memory cell array groups, when a defect column exists in a memory cell array included in any of said plurality of memory cell array groups, said coincidence/non-coincidence detecting means reading data from a corresponding column to be replaced in said redundant memory cell array through said redundancy reading line, instead of reading data from the defect column in the memory cell array group including the defect column.

Claim 22

A semiconductor memory device, comprising: a first memory cell array group including at least one memory cell array; a second memory cell array group including at least one memory cell array, each memory cell array included in said first and second memory cell array groups including memory cells arranged in rows and columns; a plurality of first data reading lines provided correspondingly to said first memory cell array group, for transferring multi-bit data from a memory cell array included in the first memory cell array group; a plurality of second data reading lines provided correspondingly to said second memory cell array group, for transferring multi-bit data from a memory cell array included in the second memory cell array group; a single redundant memory cell array block provided in common for said first and second memory cell array groups, for replacing an arbitrary defect column in all the memory cell arrays included in said first and second memory cell array groups, said redundant memory cell array block including redundant memory cells arranged in rows and columns; a redundancy data reading line connected to said redundant memory cell array block for transferring one-bit data from the redundant memory cell array; defect address storage means for storing a defect address signal indicating a defective portion in said memory cell array; address coincidence detecting means for detecting a coincidence of an externally applied address signal and the defect address signal stored in said defect address storage means; redundant access means responsive to said address coincidence defecting means for accessing said redundant memory cell array in place of said memory cell array including said defective portion; test mode detecting means for detecting a designation of an external test mode; and coincidence/non-coincidence detecting means responsive to said test mode detecting means, for detecting a coincidence/non-coincidence of multi-bit data read from a memory cell array of said first memory cell group through said first data reading lines, and multi-bit data reading from a memory cell array of said second memory cell array group through said second data reading lines, when a defect column exists in a memory cell array included in either of said first and second memory cell array groups, said coincidence/non-coincidence detecting means reading one-bit data from a corresponding column to be replaced in said redundant memory cell array through said redundancy reading line, instead of reading one-bit data from a defect column of the memory cell array group including the defect column.

Claim 23

A semiconductor memory device, comprising: a first memory cell array group including at least one memory cell array; a second memory cell array group including at least one memory cell array, each memory cell array included in said first and second memory cell array groups including memory cells arranged in rows and columns; a plurality of first data reading lines provided correspondingly to said first memory cell array group, for transferring multi-bit data from a memory cell array included in the first memory cell array group; a plurality of second data reading lines provided correspondingly to said second memory cell array group, for transferring multi-bit data from a memory cell array included in the second memory cell array group; a single redundant memory cell array block provided in common for said first and second memory cell array groups, for replacing an arbitrary defect column in all the memory cell arrays included in said first and second memory cell array groups, said redundant memory cell array block including redundant memory cells arranged in rows and columns; a redundancy data reading line connected to said redundant memory cell array block for transferring one-bit data from the redundant memory cell array; defect address storage means for storing a defect address signal indicating a defective portion in said memory cell array; address coincidence detecting means for detecting a coincidence of an externally applied address signal and the defect address signal stored in said defect address storage means; redundant access means responsive to said address coincidence defecting means for accessing said redundant memory cell array in place of said memory cell array including said defective portion; test mode detecting means for detecting a designation of an external test mode; and coincidence/non-coincidence detecting means responsive to said test mode detecting means, for detecting a coincidence/non-coincidence of multi-bit data read from a memory cell array of said first memory cell group through said first data reading lines, and multi-bit data reading from a memory cell array of said second memory cell array group through said second data reading lines, when a defect column exists in a memory cell array included in either of said first and second memory cell array groups, said coincidence/non-coincidence detecting means reading one-bit data from a corresponding column to be replaced in said redundant memory cell array through said redundancy reading line, instead of reading one-bit data from a defect column of the memory cell array group including the defect column.

Claim 24

A semiconductor memory device, comprising: a first memory cell array group including at least one memory cell array; a second memory cell array group including at least one memory cell array, each memory cell array included in said first and second memory cell array groups including memory cells arranged in rows and columns; a plurality of first data reading lines corresponding to said first memory cell array group, for transferring multi-bit data from a memory cell array included in the first memory cell array group; a plurality of second data reading lines provided corresponding to said second memory cell array group, for transferring multi-bit data from a memory cell array included in the second memory cell array group; a single redundant memory cell array block provided in common for said first and second memory cell array groups, for replacing an arbitrary defect column in all the memory cell arrays included in said first and second memory cell array groups, said redundant memory cell array block including redundant memory cells arranged in rows and columns; a redundancy data reading line connected to said redundant memory cell array block for transferring one-bit data from the redundant memory cell array; detect address storage means for storing a defect address signal indicating a defective portion in said memory cell array; address coincidence detecting means for detecting a coincidence of an externally applied address signal and the defective address signal stored in said defect address storage means; and redundant access means responsive to said address coincidence detecting means for accessing said redundant memory cell array in place of said memory cell array including said defective portion.

Claim 25

A semiconductor memory device, comprising: a first memory cell array group including at least one memory cell array; a second memory cell array group including at least one memory cell array, each memory cell array included in said first and second memory cell array groups including memory cells arranged in rows and columns; a plurality of first data reading lines corresponding to said first memory cell array group, for transferring multi-bit data from a memory cell array included in the first memory cell array group; a plurality of second data reading lines provided corresponding to said second memory cell array group, for transferring multi-bit data from a memory cell array included in the second memory cell array group; a single redundant memory cell array block provided in common for said first and second memory cell array groups, for replacing an arbitrary defect column in all the memory cell arrays included in said first and second memory cell array groups, said redundant memory cell array block including redundant memory cells arranged in rows and columns; a redundancy data reading line connected to said redundant memory cell array block for transferring one-bit data from the redundant memory cell array; detect address storage means for storing a defect address signal indicating a defective portion in said memory cell array; address coincidence detecting means for detecting a coincidence of an externally applied address signal and the defective address signal stored in said defect address storage means; and redundant access means responsive to said address coincidence detecting means for accessing said redundant memory cell array in place of said memory cell array including said defective portion.