Patent US5789285A successfully refreshed from Google Patents.
US5789285A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Manufacturing method for BIMOS
Assignee: Sony Corp
•
Filing: 1996-09-27
•
Granted: 1998-08-04
•
Expires: 2016-09-27
Abstract
Abstract In a BiMOS semiconductor device, emitter and base electrodes formed by polycrystalline Si of a bipolar transistor are isolated from each other by way of a sidewall and an insulator layer. As this insulator layer acts as an offset during the formation of the sidewall, its layer thickness can be made larger. Further, as this insulator layer is not provided in a MOS region, its step can be made smaller. Consequently, parasitic capacitance can be reduced while the insulator layer can be made thicker. Thus, there can be achieved both fast operation and high reliability of the bipolar transistor and, moreover, reduction in the reliability of a MOS transistor can also be prevented.
Inventors
- 👤 Ikuo Yoshihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:07
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; Y; Y10; Y10S; Y10S148/00; Y10S148/009
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
147 words
A manufacturing method of BiMOS semiconductor device comprising a bipolar transistor and a MOS transistor in a common semiconductor base, comprising the steps of: forming at least one MOS transistor transistor on the semiconductor base; forming a first insulator layer over the MOS transistor and over a first region of the bipolar transistor; forming a contact opening in the first insulator layer; forming a first electrode for the first region of the bipolar transistor in the contact opening, the first electrode being an etching stopper layer; forming a second insulator layer covering the contact opening and the first electrode; forming an opening portion in the second insulator, the opening portion being contained within the contact opening; forming a sidewall within said opening portion; and forming a second electrode within the opening portion over the sidewall; wherein the second insulator layer does not extend over the MOS transistor.
Claim 2
Dependent Claim
147 words
A manufacturing method of BiMOS semiconductor device comprising a bipolar transistor and a MOS transistor in a common semiconductor base, comprising the steps of: forming at least one MOS transistor transistor on the semiconductor base; forming a first insulator layer over the MOS transistor and over a first region of the bipolar transistor; forming a contact opening in the first insulator layer; forming a first electrode for the first region of the bipolar transistor in the contact opening, the first electrode being an etching stopper layer; forming a second insulator layer covering the contact opening and the first electrode; forming an opening portion in the second insulator, the opening portion being contained within the contact opening; forming a sidewall within said opening portion; and forming a second electrode within the opening portion over the sidewall; wherein the second insulator layer does not extend over the MOS transistor.
Claim 3
Dependent Claim
20 words
The manufacturing method of BiMOS semiconductor device according to claim 1, wherein said etching stopper layer comprises a semiconductor layer.
Claim 4
Dependent Claim
20 words
The manufacturing method of BiMOS semiconductor device according to claim 1, wherein the etching stopper layer comprises a base electrode.
Claim 5
Dependent Claim
25 words
The manufacturing method of BiMOS semiconductor device according to claim 1, wherein the etching stopper layer comprises a polycrystalline Si layer on a base electrode.
Claim 6
Dependent Claim
47 words
The method as set forth in claim 1, wherein the step of forming the second insulator layer comprises a step of forming the second insulator layer over the MOS transistor and the method further comprises a step of etching the second insulator layer from the MOS transistor.
Claim 7
Dependent Claim
26 words
The method as set forth in claim 5, wherein the step of etching comprises a step of using the first electrode as the etching stopper layer.
Claim 8
Dependent Claim
27 words
The method as set forth in claim 5, wherein the step of forming the first insulator layer comprises a step of forming a pair of interlayer insulators.
Claim 9
Dependent Claim
24 words
The method as set forth in claim 5, wherein the step of forming the first electrode comprises a step of forming a base electrode.
Claim 10
Dependent Claim
24 words
The method as set forth in claim 5, wherein the step of forming the second electrode comprises a step of forming an emitter electrode.
References Cited (Backward Citations)
EP0339637A2
Cited
US5204276A
Cited
US4994400A
Cited
US5091322A
Cited
US5202273A
Cited
EP0495329A2
Cited
US5132234A
Cited
US5324672A
Cited
DE4230858A1
Cited
US5319234A
Cited
JPH0677418A
Cited
JPH06181292A
Cited
US5403758A
Cited
US5541124A
Cited
US5439833A
Cited
US5604374A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-03 | 2002-02-02 | 2002-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-03 | 2006-02-02 | 2006-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-03 | 2010-02-02 | 2010-08-04 | $7700.00 | Window Closed / Lapsed |