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US5324672A Expired / Lapsed US ⏱️ 0.0 years remaining

Manufacturing method for bipolar transistor

Assignee: Sony Corp
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Filing: 1992-10-23
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Granted: 1994-06-28
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Expires: 2012-10-23
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Abstract

Abstract A bipolar transistor including a semiconductor layer formed on a semiconductor substrate; a base region formed at an upper portion of the semiconductor layer; a graft base region formed at the upper portion of the semiconductor layer so as to connect with a periphery of the base region; an emitter region formed at an upper portion of the base region; an offset insulating film formed on the base region around the emitter region; a collector buried region formed in the semiconductor layer below the base region; a collector drawn region formed in the semiconductor layer so as to connect with the collector buried region and be arranged on the side of the base region adjacent to an element isolating region; an emitter electrode formed on the offset insulating film so as to connect with the emitter region; an emitter insulating film formed so as to cover the emitter electrode; a base electrode formed so as to connect with the graft base region and contact with the emitter insulating film; and a collector electrode formed so as to connect with the collector drawn region.

Inventors

  • 👤 Hiroaki Anmo
  • 👤 Hiroyuki Miwa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 15:30
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/01

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 353 words
A manufacturing method for a bipolar transistor, comprising: the first step of forming a collector buried region at an upper portion of a semiconductor substrate, forming a semiconductor layer on an upper surface of said semiconductor substrate, forming an element isolating region in said semiconductor layer, forming a first insulating film at an upper portion of said semiconductor layer, and forming a first polysilicon film on an entire upper surface-of said semiconductor layer so as to cover said first insulating film; the second step of forming a mask pattern from said first polysilicon film on a base forming region around an emitter forming region, and etching said first polysilicon film with said mask pattern used as an etching mask to form an offset insulating film from said first insulating film; the third step of forming a second polysilicon film on the entire upper surface of said semiconductor layer so as to cover said mask pattern, forming a second insulating film on an entire upper surface of said second polysilicon film, and etching said second insulating film and said second polysilicon film to form an emitter electrode from said second polysilicon film; the fourth step of forming an emitter side wall insulating film on a side wall of said emitter electrode to form an emitter insulating film constituted of said emitter side wall insulating film and said second Insulating film formed on an upper surface of said emitter electrode; the fifth step of forming a graft base region at an upper portion of said semiconductor layer on both sides of said base forming region, and forming a collector drawn region in said semiconductor layer so that said collector drawn region connects with said collector buried region and is arranged on the side of said base forming region adjacent to said element isolating region; and the sixth step of forming a base region in said base forming region, forming an emitter region in said emitter forming region, and forming a base electrode connecting with said graft base region and contacting with said emitter insulating film and a collector electrode connecting with said collector drawn region.
Claim 2
Dependent Claim 353 words
A manufacturing method for a bipolar transistor, comprising: the first step of forming a collector buried region at an upper portion of a semiconductor substrate, forming a semiconductor layer on an upper surface of said semiconductor substrate, forming an element isolating region in said semiconductor layer, forming a first insulating film at an upper portion of said semiconductor layer, and forming a first polysilicon film on an entire upper surface-of said semiconductor layer so as to cover said first insulating film; the second step of forming a mask pattern from said first polysilicon film on a base forming region around an emitter forming region, and etching said first polysilicon film with said mask pattern used as an etching mask to form an offset insulating film from said first insulating film; the third step of forming a second polysilicon film on the entire upper surface of said semiconductor layer so as to cover said mask pattern, forming a second insulating film on an entire upper surface of said second polysilicon film, and etching said second insulating film and said second polysilicon film to form an emitter electrode from said second polysilicon film; the fourth step of forming an emitter side wall insulating film on a side wall of said emitter electrode to form an emitter insulating film constituted of said emitter side wall insulating film and said second Insulating film formed on an upper surface of said emitter electrode; the fifth step of forming a graft base region at an upper portion of said semiconductor layer on both sides of said base forming region, and forming a collector drawn region in said semiconductor layer so that said collector drawn region connects with said collector buried region and is arranged on the side of said base forming region adjacent to said element isolating region; and the sixth step of forming a base region in said base forming region, forming an emitter region in said emitter forming region, and forming a base electrode connecting with said graft base region and contacting with said emitter insulating film and a collector electrode connecting with said collector drawn region.
Claim 3
Dependent Claim 368 words
A manufacturing method for a bipolar transistor, comprising: the first step of forming a collector buried region at an upper portion of a semiconductor substrate, forming a semiconductor layer on an upper surface of said semiconductor substrate, forming a first insulating film at an upper portion of said semiconductor layer, and forming a first polysilicon film on an entire upper surface of said semiconductor layer so as to cover said first insulating film; the second step of forming a mask pattern from said first polysilicon film on a base forming region around an emitter forming region, and etching said first polysilicon film with said mask pattern used as an etching mask to form an offset insulating film from said first insulating film; the third step of forming a second polysilicon film on the entire upper surface of said semiconductor layer so as to cover said mask pattern, forming a second insulating film on an entire upper surface of said second polysilicon film, and etching said second insulating film and said second polysilicon film to form an emitter electrode from said second polysilicon film; the fourth step of forming an emitter side wall insulating film on a side wall of said emitter electrode to form an emitter insulating film constituted of said emitter side wall insulating film and said second insulating film formed on an upper surface of said emitter electrode; the fifth step of forming a graft base region at an upper portion of said semiconductor layer on one side of said base forming region, and forming a collector drawn region in said semiconductor layer so that said collector drawn region connects with said collector buried region and is arranged on the other side of said base forming region adjacent to a portion of said semiconductor layer connecting with said base forming region; and the sixth step of forming a base region in said base forming region, forming an emitter region in said emitter forming region, and forming a base electrode connecting with said graft base region and contacting with one side of said emitter insulating film and a collector electrode connecting with said collector drawn region and contacting with the other side of said emitter insulating film.
Claim 4
Dependent Claim 368 words
A manufacturing method for a bipolar transistor, comprising: the first step of forming a collector buried region at an upper portion of a semiconductor substrate, forming a semiconductor layer on an upper surface of said semiconductor substrate, forming a first insulating film at an upper portion of said semiconductor layer, and forming a first polysilicon film on an entire upper surface of said semiconductor layer so as to cover said first insulating film; the second step of forming a mask pattern from said first polysilicon film on a base forming region around an emitter forming region, and etching said first polysilicon film with said mask pattern used as an etching mask to form an offset insulating film from said first insulating film; the third step of forming a second polysilicon film on the entire upper surface of said semiconductor layer so as to cover said mask pattern, forming a second insulating film on an entire upper surface of said second polysilicon film, and etching said second insulating film and said second polysilicon film to form an emitter electrode from said second polysilicon film; the fourth step of forming an emitter side wall insulating film on a side wall of said emitter electrode to form an emitter insulating film constituted of said emitter side wall insulating film and said second insulating film formed on an upper surface of said emitter electrode; the fifth step of forming a graft base region at an upper portion of said semiconductor layer on one side of said base forming region, and forming a collector drawn region in said semiconductor layer so that said collector drawn region connects with said collector buried region and is arranged on the other side of said base forming region adjacent to a portion of said semiconductor layer connecting with said base forming region; and the sixth step of forming a base region in said base forming region, forming an emitter region in said emitter forming region, and forming a base electrode connecting with said graft base region and contacting with one side of said emitter insulating film and a collector electrode connecting with said collector drawn region and contacting with the other side of said emitter insulating film.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-06-27 1997-12-27 1998-06-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-06-27 2001-12-27 2002-06-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-06-27 2005-12-27 2006-06-28 $7700.00 Window Closed / Lapsed

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