Static memory cell and method of manufacturing a static memory cell

Claim 2

A memory device comprising: a static random access memory cell including a p-type semiconductor substrate; an n-type region in the substrate; an n-channel transistor formed over the n-type region, the n-channel transistor having a source defining a memory node, a gate, and a drain; the memory node, the n-type region, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the memory node acting as the collector of the parasitic transistor, and the n-type region acting as the emitter of the parasitic transistor; and a p+ region in junction relation with the source and operating in combination with the source to define a tunnel diode, the p-type semiconductor substrate being forward biased relative to the n-type region, and the parasitic transistor being forward biased to act as a current sink for the memory node.

Claim 3

A memory device in accordance with claim 1 wherein the memory node includes a lowermost portion which is ≦0.1 micron above the n-type region.

Claim 4

A memory device in accordance with claim 1 wherein the memory node includes a lowermost portion which is ≦0.4 micron above the n-type region.

Claim 5

A memory device comprising: a static random access memory cell including a p-type semiconductor substrate comprising material having an average dopant concentration of at least 1×10 16 ions/cm 3 ; an n-type region in the substrate; an n-channel transistor formed over the n-type region, the n-channel transistor having a source defining a memory node, a gate, and a drain; the memory node, the n-type region, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the memory node acting as the collector of the parasitic transistor, and the n-type region acting as the emitter of the parasitic transistor; and a p+ region in junction relation with the memory node and operating in combination with the memory node to define a tunnel diode, the region in junction relation with the memory node comprising epitaxial silicon grown over the source.

Claim 6

A memory device comprising: a static random access memory cell including a p-type semiconductor substrate comprising material having an average dopant concentration of at least 1×10 16 ions/cm 3 ; an n-type region in the substrate; an n-channel transistor formed over the n-type region, the n-channel transistor having a source defining a memory node, a gate, and a drain; the memory node, the n-type region, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the memory node acting as the collector of the parasitic transistor, and the n-type region acting as the emitter of the parasitic transistor; and a p+ region in junction relation with the memory node and operating in combination with the memory node to define a tunnel diode, the region in junction relation with the memory node comprising epitaxial silicon grown over the source.

Claim 7

A memory device comprising: a static random access memory cell including a p-type semiconductor substrate comprising material having an average dopant concentration of at least 1×10 6 ions/cm 3 ; an n-type region in the substrate, an n-channel transistor formed over the n-type region, the n-channel transistor having a source defining a memory node, a gate, and a drain; the memory node, the n-type region, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the memory node acting as the collector of the parasitic transistor, and the n-type region acting as the emitter of the parasitic transistor; and a p+ region in function relation with the memory node and operating in combination with the memory node to define a tunnel diode, the region in junction relation with the memory node comprising an implant in the memory node.

Claim 8

A memory device comprising: a static random access memory cell including a p-type semiconductor substrate comprising material having an average dopant concentration of at least 1×10 6 ions/cm 3 ; an n-type region in the substrate, an n-channel transistor formed over the n-type region, the n-channel transistor having a source defining a memory node, a gate, and a drain; the memory node, the n-type region, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the memory node acting as the collector of the parasitic transistor, and the n-type region acting as the emitter of the parasitic transistor; and a p+ region in function relation with the memory node and operating in combination with the memory node to define a tunnel diode, the region in junction relation with the memory node comprising an implant in the memory node.

Claim 9

A memory device comprising: a static random access memory cell including an n-type semiconductor substrate; a p-type region in the substrate; a p-channel transistor formed over the p-type region, the p-channel transistor having a source defining a memory node, a gate, and a drain; the memory node, the p-type region, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the memory node acting as the collector of the parasitic transistor, and the p-type region acting as the emitter of the parasitic transistor; and an n+ region in junction relation with the source and operating in combination with the source to define a tunnel diode, wherein, in operation, the n-type semiconductor substrate is connected to a first voltage, the p-type region is connected to a second voltage above the first voltage, the n+ region is connected to a third voltage lower than the first voltage, and the parasitic transistor is forward biased to act as a current sink for the memory node.

Claim 10

A memory device comprising: a static random access memory cell including an n-type semiconductor substrate; a p-type region in the substrate; a p-channel transistor formed over the p-type region, the p-channel transistor having a source defining a memory node, a gate, and a drain; the memory node, the p-type region, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the memory node acting as the collector of the parasitic transistor, and the p-type region acting as the emitter of the parasitic transistor; and an n+ region in junction relation with the source and operating in combination with the source to define a tunnel diode, wherein, in operation, the n-type semiconductor substrate is connected to a first voltage, the p-type region is connected to a second voltage above the first voltage, the n+ region is connected to a third voltage lower than the first voltage, and the parasitic transistor is forward biased to act as a current sink for the memory node.

Claim 11

A static random access memory cell comprising: a substrate; exactly one MOSFET, the MOSFET of the memory cell being formed over the substrate, the MOSFET having a gate, a drain, and a source; a first region in the substrate, under the source; and a second region in junction relation with the source and operating with the source as a tunnel diode, the source, the first region, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the source acting as the collector of the parasitic transistor, and the first region acting as the emitter of the parasitic transistor.

Claim 12

A static random access memory cell comprising: a substrate; exactly one MOSFET, the MOSFET of the memory cell being formed over the substrate, the MOSFET having a gate, a drain, and a source; a first region in the substrate, under the source; and a second region in junction relation with the source and operating with the source as a tunnel diode, the source, the first region, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the source acting as the collector of the parasitic transistor, and the first region acting as the emitter of the parasitic transistor.

Claim 13

A static random access memory cell comprising: a substrate; exactly one MOSFET formed over the substrate, the MOSFET having a gate, a drain, and a source; a first region in the substrate, under the source; and a region in junction relation with the source and operating with the source as a tunnel diode, the source, the first region, and the substrate defining a parasitic transistor that operates with the MOSFET to maintain data in the memory cell without need for refreshing.

Claim 14

A static random access memory cell comprising: a substrate; exactly one MOSFET formed over the substrate, the MOSFET having a gate, a drain, and a source; a first region in the substrate, under the source; and a region in junction relation with the source and operating with the source as a tunnel diode, the source, the first region, and the substrate defining a parasitic transistor that operates with the MOSFET to maintain data in the memory cell without need for refreshing.

Claim 15

A static random access memory cell comprising: a p-type semiconductor substrate having an average p-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried n-type diffusion region in the substrate, the n-type region having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage lower than the first voltage; an n-channel transistor formed relative to the substrate over the n-type region, the n-channel transistor having a source, a gate, and a drain, the source having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and the drain having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 ; and a p-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the p-type region being connected to a third voltage higher than the first voltage, the source, the n-type region, and the substrate defining a transistor with the substrate acting as the base of the transistor, the memory node acting as the collector of the transistor, and the n-type region acting as the emitter of the transistor.

Claim 16

A static random access memory cell comprising: a p-type semiconductor substrate having an average p-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried n-type diffusion region in the substrate, the n-type region having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage lower than the first voltage; an n-channel transistor formed relative to the substrate over the n-type region, the n-channel transistor having a source, a gate, and a drain, the source having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and the drain having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 ; and a p-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the p-type region being connected to a third voltage higher than the first voltage, the source, the n-type region, and the substrate defining a transistor with the substrate acting as the base of the transistor, the memory node acting as the collector of the transistor, and the n-type region acting as the emitter of the transistor.

Claim 17

A static memory cell comprising: an n-type semiconductor substrate having an average n-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried p-type diffusion region in the substrate, the p-type region having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage above the first voltage; a p-channel transistor formed relative to the substrate over the p-type region, the p-channel transistor having a source, a gate, and a drain, the source having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and the drain having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 ; and an n-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the n-type region being connected to a third voltage lower than the first voltage, the source, the p-type region, and the substrate defining a transistor with the substrate acting as the base of the transistor, the memory node acting as the collector of the transistor, and the p-type region acting as the emitter of the transistor.

Claim 18

A static memory cell comprising: an n-type semiconductor substrate having an average n-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried p-type diffusion region in the substrate, the p-type region having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage above the first voltage; a p-channel transistor formed relative to the substrate over the p-type region, the p-channel transistor having a source, a gate, and a drain, the source having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and the drain having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 ; and an n-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the n-type region being connected to a third voltage lower than the first voltage, the source, the p-type region, and the substrate defining a transistor with the substrate acting as the base of the transistor, the memory node acting as the collector of the transistor, and the p-type region acting as the emitter of the transistor.

Claim 19

A memory device comprising: a static random access memory cell including a p-type semiconductor substrate; a n-type region in the substrate; exactly one n-channel transistor, the n-channel transistor being formed over the n-type region, the n-channel transistor having a control electrode and two power electrodes, one of the power electrodes defining a memory node; the memory node, the n-type region, and the substrate defining a transistor with the substrate acting as the base of the transistor, the memory node acting as the collector of the transistor, and the n-type region acting as the emitter of the transistor; and a p+ region in junction relation with the memory node and operating in combination with the memory node to define a tunnel diode.

Claim 20

A memory device comprising: a static random access memory cell including a p-type semiconductor substrate; a n-type region in the substrate; exactly one n-channel transistor, the n-channel transistor being formed over the n-type region, the n-channel transistor having a control electrode and two power electrodes, one of the power electrodes defining a memory node; the memory node, the n-type region, and the substrate defining a transistor with the substrate acting as the base of the transistor, the memory node acting as the collector of the transistor, and the n-type region acting as the emitter of the transistor; and a p+ region in junction relation with the memory node and operating in combination with the memory node to define a tunnel diode.

Claim 21

A memory device comprising: a static random access memory cell including an n-type semiconductor substrate; a p-type region in the substrate; exactly one p-channel transistor, the p-channel transistor being formed over the p-type region, the p-channel transistor having a control electrode and two power electrodes, one of the power electrodes defining a memory node; the memory node, the p-type region, and the substrate defining a transistor with the substrate acting as the base of the transistor, the memory node acting as the collector of the transistor, and the p-type region acting as the emitter of the transistor; and an n+ region in junction relation with the memory node and operating in combination with the memory node to define a tunnel diode.

Claim 22

A memory device comprising: a static random access memory cell including an n-type semiconductor substrate; a p-type region in the substrate; exactly one p-channel transistor, the p-channel transistor being formed over the p-type region, the p-channel transistor having a control electrode and two power electrodes, one of the power electrodes defining a memory node; the memory node, the p-type region, and the substrate defining a transistor with the substrate acting as the base of the transistor, the memory node acting as the collector of the transistor, and the p-type region acting as the emitter of the transistor; and an n+ region in junction relation with the memory node and operating in combination with the memory node to define a tunnel diode.

Claim 23

A memory device in accordance with claim 4 wherein the region in junction relation with the source comprises material having an average dopant concentration of at least 1×10 19 .

Claim 24

A memory device in accordance with claim 5 wherein the region in junction relation with the source comprises material having an average dopant concentration of at least 1×10 19 .