US5084401A
Expired / Lapsed
US
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Insulated gate bipolar transistor and method of manufacturing the same
Assignee: Mitsubishi Electric Corp
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Filing: 1990-12-17
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Granted: 1992-01-28
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Expires: 2010-12-17
Abstract
Abstract A P-type base region, which is formed on an N-type body layer, as a relatively deep first base region and a relatively shallow second base region. An N + -type emitter region is formed on the base region. A portion of the surface of the second base region between surfaces of the emitter region and body layer is defined as a channel. A gate oxide film, on which a gate electrode is formed, is provided on the channel. The amount and depth of introduction of an impurity in the second base region is about 2×10 14 to 5×10 14 cm -2 and 4 to 10 μm, respectively. The thickness of the gate oxide film is about 600 to 1000 Å. Thus, an IGBT is implemented, which can ensure sufficient pulse energization ability while causing no latch-up in application to a stroboscope circuit.
Inventors
- 👤 Hiroyasu Hagino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 18:49
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/411; H10D12/441; H10D62/00; H10D62/10; H10D62/17; H10D62/393
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
273 words
A method of manufacturing an insulated gate bipolar transistor, comprising the steps of: preparing a first conductivity type first semiconductor layer having first and second major surfaces; forming a second conductivity type second semiconductor layer on said first major surface of said first semiconductor layer; selectively introducing a first conductivity type impurity into said second semiconductor layer to form a relatively deep first conductivity type first semiconductor region on said second semiconductor layer; forming an oxide film having a thickness of about 600 to 1000 Å on said second semiconductor layer and said first semiconductor region; forming a conductor layer on said oxide film; patterning said oxide film and said conductor layer to define a window; introducing a first conductivity type impurity into said second semiconductor layer in an impurity dose amount of about 2×10 14 to 5×10 14 cm -2 through said window to form a first conductivity type second semiconductor region having relatively shallow depth of about 4 to 10 μm, said first and second semiconductor regions being adjacent to each other and integrated to form a first conductivity type well region; selectively introducing a second conductivity type impurity into said well region through said window to form a second conductivity type third semiconductor region on said well region; selectively removing said oxide film and said conductor layer while at least leaving portions thereof on a portion of a surface of said second semiconductor region between surfaces of said third semiconductor region and said second semiconductor layer; forming a first electrode on said third semiconductor region; and forming a second electrode on said second major surface of said first semiconductor layer.
Claim 2
Independent Claim
273 words
A method of manufacturing an insulated gate bipolar transistor, comprising the steps of: preparing a first conductivity type first semiconductor layer having first and second major surfaces; forming a second conductivity type second semiconductor layer on said first major surface of said first semiconductor layer; selectively introducing a first conductivity type impurity into said second semiconductor layer to form a relatively deep first conductivity type first semiconductor region on said second semiconductor layer; forming an oxide film having a thickness of about 600 to 1000 Å on said second semiconductor layer and said first semiconductor region; forming a conductor layer on said oxide film; patterning said oxide film and said conductor layer to define a window; introducing a first conductivity type impurity into said second semiconductor layer in an impurity dose amount of about 2×10 14 to 5×10 14 cm -2 through said window to form a first conductivity type second semiconductor region having relatively shallow depth of about 4 to 10 μm, said first and second semiconductor regions being adjacent to each other and integrated to form a first conductivity type well region; selectively introducing a second conductivity type impurity into said well region through said window to form a second conductivity type third semiconductor region on said well region; selectively removing said oxide film and said conductor layer while at least leaving portions thereof on a portion of a surface of said second semiconductor region between surfaces of said third semiconductor region and said second semiconductor layer; forming a first electrode on said third semiconductor region; and forming a second electrode on said second major surface of said first semiconductor layer.
Claim 3
Dependent Claim
92 words
A method of manufacturing an insulated gate bipolar transistor in accordance with claim 1, further comprising the steps of: selectively removing said oxide film and said conductor layer to open a further window, after formation of said second semiconductor region; and introducing a first conductivity type impurity into said well region in impurity dose amount of about 0.8×10 15 to 1×10 15 cm -2 through said further window to form first conductivity type fourth semiconductor region of about half depth of said second semiconductor region on a center of said well region.
References Cited (Backward Citations)
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