Distributed placement, variable-size cache architecture

Claim 2

A distributed placement architecture associated with a single processor interface for distributing and retrieving information comprising: a variable-size, singular cache having plural cache storage units (CSUs) therein, wherein each CSU includes a set associative memory having at least one memory element for storing information, wherein the number of elements within each set of the set associative memory is variable, thereby providing said variable size cache, and which further includes a distribution controller, said distribution controller being configured to collectively distribute within and receive information from the cache by selecting an individual CSU for placement and/or retrieval of information and for controlling placement of data among the plural CSUs and within individual CSUs, wherein said distribution controller includes a placement mechanism which distributes data within said set associative memory to individual memory elements depending on the placement of said memory element within said set associative memory, wherein the number of CSUs is variable, and wherein said CSU is insertable into said variable-size cache without re-configuring the connectivity or settings of said variable-size cache; a communications network between said plural CSUs operatively connecting each CSU directly to each of the other CSUs, said communications network providing a CSU-associated indication signal to all cache storage units within the singular cache, wherein such signal indicates a cache hit in one of said plural CSUs and identifies that one; wherein said distribution controller is operatively connected to said communications network for sensing and selecting a CSU in which to place information.

Claim 3

The architecture of claim 1 wherein each CSU includes: a set associative memory having at least one element block, an address director, a placement logic, a placement array, a data director and a control logic.

Claim 4

The architecture of claim 2 further comprising a distribution controller, operatively connected to said communications network, for selecting individual CSUs in which to place information.

Claim 5

The architecture of claim 3 wherein said distribution controller includes a placement mechanism for controlling the distributions of information within the cache to individual CSUs according to a CSU placement algorithm and depending on the placement of said individual CSU within the architecture.

Claim 6

The architecture of claim 3 wherein said distribution controller includes a placement mechanism which controls the distribution of information within said set associative memory to individual element blocks according to an internal placement algorithm and depending on the placement of said element block within the set associative memory.

Claim 7

The architecture of claim 5 wherein said placement mechanism includes a CSU status monitor for monitoring the placement state of an individual CSU relative to the placement state of other CSUs in the architecture.

Claim 8

The architecture of claim 6 wherein said placement mechanism is constructed and arranged to place information within an individual CSU when said individual CSU determines that it is a placement CSU.

Claim 9

The architecture of claim 1 which includes a secondary TAG in each CSU.

Claim 10

A distributed cache placement architecture associated with a single processor interface for distributing and retrieving information comprising: a variable-size, singular cache having plural cache storage units (CSUs) therein, wherein each CSU includes a set associative memory having at least one element block, wherein said set associative memory is constructed and arranged to allow insertion and removal of element blocks to vary the size of said variable-size cache without reconfiguration of said variable-size cache, an address director, a placement logic, a placement array, a data director and a control logic; a communications network between said plural CSUs said communications network providing a CSU-associated indication signal to all CSUs within the singular cache, wherein such signal indicates a cache hit in one of said plural CSUs and identifies that one and said communications network includes a HIT line connecting all CSUs in the architecture; a distribution controller operatively connected to said communications network, for sensing and selecting an individual CSU in which to place data, wherein said distribution controller includes a placement mechanism which distributes data within said set associative memory to individual memory elements depending on the placement of said memory element within said set associative memory; and a CSU status monitor for monitoring the placement state of an individual CSU relative to the placement state of other CSUs in the architecture.

Claim 11

A distributed cache placement architecture associated with a single processor interface for distributing and retrieving information comprising: a variable-size, singular cache having plural cache storage units (CSUs) therein, wherein each CSU includes a set associative memory having at least one element block, wherein said set associative memory is constructed and arranged to allow insertion and removal of element blocks to vary the size of said variable-size cache without reconfiguration of said variable-size cache, an address director, a placement logic, a placement array, a data director and a control logic; a communications network between said plural CSUs said communications network providing a CSU-associated indication signal to all CSUs within the singular cache, wherein such signal indicates a cache hit in one of said plural CSUs and identifies that one and said communications network includes a HIT line connecting all CSUs in the architecture; a distribution controller operatively connected to said communications network, for sensing and selecting an individual CSU in which to place data, wherein said distribution controller includes a placement mechanism which distributes data within said set associative memory to individual memory elements depending on the placement of said memory element within said set associative memory; and a CSU status monitor for monitoring the placement state of an individual CSU relative to the placement state of other CSUs in the architecture.

Claim 12

The architecture of claim 9 wherein said set associative memory includes a primary TAG therein and wherein said plural CSUs each includes a secondary TAG.

Claim 13

The architecture of claim 9 wherein said distribution controller includes a placement mechanism for controlling the distributions of information within the cache to individual CSUs according to a CSU placement algorithm and depending on the placement of said individual CSU within the architecture.

Claim 14

The architecture of claim 9 wherein said distribution controller includes a placement mechanism which controls the distribution of information within said set associative memory to individual element blocks according to an internal placement algorithm and depending on the placement of said element block within the set associative memory.

Claim 15

The architecture of claim 9 wherein said placement mechanism includes a CSU status monitor for monitoring the placement state of an individual CSU relative to the placement state of other CSUs in the architecture.

Claim 16

The architecture of claim 13 wherein said placement mechanism is constructed and arranged to place information within an individual CSU when said individual CSU determines that it is a placement CSU.

Claim 17

A distributed cache architecture associated with a single processor interface for distributing and retrieving information in/from a cache comprising: a variable-size cache having plural cache storage units (CSUs) therein, wherein each CSU includes a set associative memory having at least one memory element for storing information, and which further includes a distribution controller, said controllers being configured to collectively distribute within and receive information from the cache by selecting individual CSUs for placement and/or retrieval of information, wherein the number of CSUs is variable, thereby providing said variable size cache, and wherein said CSU is insertable into said variable-size cache without re-configuring the connectivity or settings of said variable-size cache; a communications network between said plural CSUs operatively connecting each CSU directly to each of the other CSUs, whereby all memory elements in said plural CSUs are interconnected so as to collectively define the singular cache, said communications network providing a CSU-associated indication signal to all CSUs, wherein such a signal indicates a cache hit in one of said plural CSUs and identifies that one, wherein the controllers of said plural CSUs are operatively interconnected via said communications network; wherein each CSU includes a distribution controller, and the controllers of said plural CSUs are operatively interconnected via said communications network, and are configured to collectively distribute within and receive information from the cache by sensing and selecting individual CSUs for placement and/or retrieval of information, wherein said distribution controller includes a placement mechanism which senses the presence of CSUs and which distributes data within said set associative memory to individual memory elements depending on the placement of said memory element within said set associative memory.

Claim 18

A distributed cache architecture associated with a single processor interface for distributing and retrieving information in/from a cache comprising: a variable-size cache having plural cache storage units (CSUs) therein, wherein each CSU includes a set associative memory having at least one memory element for storing information, and which further includes a distribution controller, said controllers being configured to collectively distribute within and receive information from the cache by selecting individual CSUs for placement and/or retrieval of information, wherein the number of CSUs is variable, thereby providing said variable size cache, and wherein said CSU is insertable into said variable-size cache without re-configuring the connectivity or settings of said variable-size cache; a communications network between said plural CSUs operatively connecting each CSU directly to each of the other CSUs, whereby all memory elements in said plural CSUs are interconnected so as to collectively define the singular cache, said communications network providing a CSU-associated indication signal to all CSUs, wherein such a signal indicates a cache hit in one of said plural CSUs and identifies that one, wherein the controllers of said plural CSUs are operatively interconnected via said communications network; wherein each CSU includes a distribution controller, and the controllers of said plural CSUs are operatively interconnected via said communications network, and are configured to collectively distribute within and receive information from the cache by sensing and selecting individual CSUs for placement and/or retrieval of information, wherein said distribution controller includes a placement mechanism which senses the presence of CSUs and which distributes data within said set associative memory to individual memory elements depending on the placement of said memory element within said set associative memory.

Claim 19

The architecture of claim 15, wherein each CSU further includes a distribution controller, and the controllers of said plural CSUs are operatively interconnected via said communications network, said controllers are configured to collectively distribute within and receive information from the cache by selecting individual CSUs for placement and/or retrieval of data.

Claim 20

The architecture of claim 15, wherein at any instant in time, not more than one distribution controller effectively controls placement and retrieval of data within/from the cache.