US5414828A
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US
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Apparatus for configuring relative position of a cache memory in a cache memory array
Assignee: Intel Corp
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Filing: 1993-07-19
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Granted: 1995-05-09
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Expires: 2013-07-19
Abstract
Abstract A cache memory which includes a cache controller formed on a single substrate. A plurality of the memories may be used in an array. The memories themselves determine how many other memories are in an array and each of their relative positions in the array. From this information, each memory sets the range of its set fields and the size of its tag fields. This is done on reset with the configuration information being distributed among the memories themselves, without being centrally stored, and in a manner transparent to the software.
Inventors
- 👤 Eran Yarkoni
- 👤 Nabeel Sakran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:42
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0669; G06F12/0676; G06F12/08; G06F12/0802; G06F12/0893; G06F2212/00; G06F2212/60; G06F2212/601
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
378 words
A cache memory for operation in a cache memory array comprising at least one cache memory, said cache memory comprising: a data storage array; selection circuit coupled to said data storage array for selecting data from said data storage array, said selection circuit for receiving an incoming address and for comparing said incoming address with stored addresses, each of said stored addresses corresponding to data in said data storage array, said selection circuit for selecting data from said data storage array based upon said comparison; logic circuit for generating a configuration signal for each cache memory in said cache memory array, wherein one configuration signal is active during each clock cycle, starting in an initial time period, for a different cache memory; configuration circuit coupled to said logic circuit for receiving a configuration signal and for sensing said configuration signal every clock cycle to count, from said initial time period, clock cycles until an active configuration signal is sensed to determine an order for said cache memory in said cache memory array, said configuration circuit for generating a ready signal, upon receipt of said active configuration signal, indicating said order of said cache memory in said cache memory array, and for sensing, each clock cycle, said ready signal, generated from a different cache memory in said cache memory array, to indicate a total number of cache memories in said cache memory array, said configuration circuit for generating at least one control signal to indicate said total number of cache memories in said cache memory array; and control circuit coupled to said selection circuit and to said configuration circuit for receiving said control signal said control circuit for utilizing n contiguous bits in said incoming address as enable bits to enable one cache memory in said cache memory array when said cache memory array comprises more than one cache memory, where n is a positive integer, and said control circuit for dynamically configuring n as a function of said control signal, and wherein one cache memory is enabled if said n contiguous bits in said incoming address correspond to a predetermined combination of n contiguous bits in said stored addresses such that only one cache memory in said cache memory array is enabled in response to said incoming address.
Claim 2
Dependent Claim
378 words
A cache memory for operation in a cache memory array comprising at least one cache memory, said cache memory comprising: a data storage array; selection circuit coupled to said data storage array for selecting data from said data storage array, said selection circuit for receiving an incoming address and for comparing said incoming address with stored addresses, each of said stored addresses corresponding to data in said data storage array, said selection circuit for selecting data from said data storage array based upon said comparison; logic circuit for generating a configuration signal for each cache memory in said cache memory array, wherein one configuration signal is active during each clock cycle, starting in an initial time period, for a different cache memory; configuration circuit coupled to said logic circuit for receiving a configuration signal and for sensing said configuration signal every clock cycle to count, from said initial time period, clock cycles until an active configuration signal is sensed to determine an order for said cache memory in said cache memory array, said configuration circuit for generating a ready signal, upon receipt of said active configuration signal, indicating said order of said cache memory in said cache memory array, and for sensing, each clock cycle, said ready signal, generated from a different cache memory in said cache memory array, to indicate a total number of cache memories in said cache memory array, said configuration circuit for generating at least one control signal to indicate said total number of cache memories in said cache memory array; and control circuit coupled to said selection circuit and to said configuration circuit for receiving said control signal said control circuit for utilizing n contiguous bits in said incoming address as enable bits to enable one cache memory in said cache memory array when said cache memory array comprises more than one cache memory, where n is a positive integer, and said control circuit for dynamically configuring n as a function of said control signal, and wherein one cache memory is enabled if said n contiguous bits in said incoming address correspond to a predetermined combination of n contiguous bits in said stored addresses such that only one cache memory in said cache memory array is enabled in response to said incoming address.
Claim 3
Dependent Claim
41 words
The cache memory defined by claim 1, wherein n equals two when said at least one control signal indicates that the total number of said cache memories in said cache memory array is greater than two but not greater than four.
Claim 4
Dependent Claim
121 words
The cache memory defined by claim 1, wherein said cache memory comprises storage for tag fields coupled to said selection circuit, each of said tag fields being part of a corresponding one of said stored addresses that is compared in said selection of data, a first number of bits of said tag fields being considered by said selection circuit in said selection of data when said control signal indicates that only one cache memory is present in said cache memory array, and wherein fewer than said first number of bits of said tag fields are considered by said selection circuit in said selection of data when said control signal indicates that said cache memory array comprises more than one cache memory.
Claim 5
Dependent Claim
29 words
The cache memory defined by claim 1, wherein n equals one when said control signal indicates that two of said cache memories are present in said cache memory array.
Claim 6
Dependent Claim
232 words
A computer system comprising: at least one processor; a cache memory array comprising at least one cache memory coupled to said processor; logic circuit for generating a configuration signal for each cache memory in said cache memory array, wherein one configuration signal is active during each clock cycle, starting in an initial time period, for a different cache memory; and a configuration circuit for each cache memory in said cache memory array coupled to said logic circuit for receiving a configuration signal and for sensing said configuration signal every clock cycle to count, from said initial time period, clock cycles until an active configuration signal is sensed to determine an order for said cache memory in said cache memory array, said configuration circuit for generating a ready signal, upon receipt of said active configuration signal, indicating said order of said cache memory in said cache memory array, and for sensing, each clock cycle, said ready signal, generated from a different cache memory in said cache memory array, to indicate a total number of cache memories in said cache memory array, said configuration circuit for generating at least one control signal to indicate said total number of cache memories in said cache memory array, wherein said control signal is utilized by each cache memory to configure said cache memory array based on said total number of cache memories in said cache memory array.
Claim 7
Dependent Claim
232 words
A computer system comprising: at least one processor; a cache memory array comprising at least one cache memory coupled to said processor; logic circuit for generating a configuration signal for each cache memory in said cache memory array, wherein one configuration signal is active during each clock cycle, starting in an initial time period, for a different cache memory; and a configuration circuit for each cache memory in said cache memory array coupled to said logic circuit for receiving a configuration signal and for sensing said configuration signal every clock cycle to count, from said initial time period, clock cycles until an active configuration signal is sensed to determine an order for said cache memory in said cache memory array, said configuration circuit for generating a ready signal, upon receipt of said active configuration signal, indicating said order of said cache memory in said cache memory array, and for sensing, each clock cycle, said ready signal, generated from a different cache memory in said cache memory array, to indicate a total number of cache memories in said cache memory array, said configuration circuit for generating at least one control signal to indicate said total number of cache memories in said cache memory array, wherein said control signal is utilized by each cache memory to configure said cache memory array based on said total number of cache memories in said cache memory array.
Claim 8
Independent Claim
270 words
A method for enabling a cache memory for operation in a cache memory array comprising at least one cache memory, said method comprising the steps of: storing data in a data storage array; generating a configuration signal for each cache memory in said cache memory array, wherein one configuration signal is active during each clock cycle, starting in an initial time period, for a different cache memory; sensing said configuration signal every clock cycle; counting, from said initial time period, clock cycles until an active configuration signal is sensed to determine an order for said cache memory in said cache memory array, generating a ready signal, upon receipt of said active configuration signal, indicating said order of said cache memory in said cache memory array; sensing, each clock cycle, said ready signal, generated from a different cache memory in said cache memory array, to indicate a total number of cache memories in said cache memory array; generating at least one control signal to indicate said total number of cache memories in said cache memory array; and receiving an incoming address; enabling one cache memory in said cache memory array by utilizing n contiguous bits, where n is a positive integer, in said incoming address as enable bits when said cache memory array comprises more than one cache memory by determining n as a function of said control signal, and enabling said cache memory if said n contiguous bits in said incoming address correspond to a predetermined combination of n contiguous bits such that only one cache memory in said cache memory array is enabled in response to said incoming address.
Claim 9
Independent Claim
270 words
A method for enabling a cache memory for operation in a cache memory array comprising at least one cache memory, said method comprising the steps of: storing data in a data storage array; generating a configuration signal for each cache memory in said cache memory array, wherein one configuration signal is active during each clock cycle, starting in an initial time period, for a different cache memory; sensing said configuration signal every clock cycle; counting, from said initial time period, clock cycles until an active configuration signal is sensed to determine an order for said cache memory in said cache memory array, generating a ready signal, upon receipt of said active configuration signal, indicating said order of said cache memory in said cache memory array; sensing, each clock cycle, said ready signal, generated from a different cache memory in said cache memory array, to indicate a total number of cache memories in said cache memory array; generating at least one control signal to indicate said total number of cache memories in said cache memory array; and receiving an incoming address; enabling one cache memory in said cache memory array by utilizing n contiguous bits, where n is a positive integer, in said incoming address as enable bits when said cache memory array comprises more than one cache memory by determining n as a function of said control signal, and enabling said cache memory if said n contiguous bits in said incoming address correspond to a predetermined combination of n contiguous bits such that only one cache memory in said cache memory array is enabled in response to said incoming address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-08 | 1998-11-07 | 1999-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-08 | 2002-11-07 | 2003-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-08 | 2006-11-07 | 2007-05-09 | $7700.00 | Window Closed / Lapsed |