US5586303A
Expired / Lapsed
US
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Structure and method for providing a cache memory of selectable sizes
Assignee: Renesas Electronics America Inc
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Filing: 1995-04-03
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Granted: 1996-12-17
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Expires: 2015-04-03
Abstract
Abstract A method and a structure provide a flexible cache module for use in cache memory performance modelling. The flexible cache module can be configured by jumper connections or switches into a cache memory having a line size and a cache size selectable from a number of combinations of line size and cache size. In addition, the flexible cache module can also be configured as either a split cache memory, for implementing separate data and instruction caches, or a unified cache memory.
Inventors
- 👤 Avigdor Willenz
- 👤 Steven M. Eliscu
- 👤 Martin E. Mueller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 02:29
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848; G06F12/0877; G06F12/0886; G06F2212/00; G06F2212/60; G06F2212/601
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
272 words
A method for configuring a variable sized cache memory, said cache memory having a data portion and a tag portion, each of said portions having a plurality of locations, addressed by a plurality of address lines, comprising the steps of: receiving into said cache memory a first set of address signals on a first group of said plurality of address lines, said first set of address signals specifying a cache memory location in said data portion of said cache memory; receiving a second set of address signals on a second group of said plurality of address lines, said second set address signals specifying a cache memory location in said tag portion of said cache memory; limiting the total number of addressable cache memory locations by setting a first number of address signals in said first set of address signals each to a predetermined logic value to limit said first set of address signals to specify a predetermined number of cache memory locations in said data portion of said cache memory; selecting a line size for said cache memory by setting a second number of address signals in said second set of address signals each to a predetermined logic value to limit said second set of address signals to specify a predetermined number of cache memory locations in said tag portion of said cache memory; and substituting one of said first set of address signals with a designated signal of said plurality of address lines to logically divide said cache memory into an instruction cache memory and a data cache memory, said designated signal indicating whether an instruction or a datum is accessed.
Claim 2
Independent Claim
272 words
A method for configuring a variable sized cache memory, said cache memory having a data portion and a tag portion, each of said portions having a plurality of locations, addressed by a plurality of address lines, comprising the steps of: receiving into said cache memory a first set of address signals on a first group of said plurality of address lines, said first set of address signals specifying a cache memory location in said data portion of said cache memory; receiving a second set of address signals on a second group of said plurality of address lines, said second set address signals specifying a cache memory location in said tag portion of said cache memory; limiting the total number of addressable cache memory locations by setting a first number of address signals in said first set of address signals each to a predetermined logic value to limit said first set of address signals to specify a predetermined number of cache memory locations in said data portion of said cache memory; selecting a line size for said cache memory by setting a second number of address signals in said second set of address signals each to a predetermined logic value to limit said second set of address signals to specify a predetermined number of cache memory locations in said tag portion of said cache memory; and substituting one of said first set of address signals with a designated signal of said plurality of address lines to logically divide said cache memory into an instruction cache memory and a data cache memory, said designated signal indicating whether an instruction or a datum is accessed.
Claim 3
Dependent Claim
317 words
A structure for configuring a variable sized cache memory addressed by a plurality of address lines, comprising: a data portion of said cache memory, said data portion of said cache memory including a plurality of cache memory locations, said data portion of said cache memory receiving a first set of address signals on a first group of address lines coupled to said plurality of address lines, said first set of address signals specifying a cache memory location in said data portion of said cache memory; a tag portion of said cache memory, said tag portion of said cache memory including a plurality of cache memory locations, said tag portion of said cache memory receiving a second set of address signals on a second group of address lines coupled to said plurality of address lines, said second set of address signals specifying a cache memory location in said tag portion of said cache memory; means for limiting the total number of addressable cache memory locations by setting a first number of address signals in said first set of address signals each to a predetermined logic value to limit said first set of address signals to specify a predetermined number of memory locations in said data portion of said cache memory; means for selecting a line size for said cache memory, said means for selecting a line size setting a second number of address signals in said second set of address signals each to predetermined logic value to limit said second set of address signals to specify a predetermined number of memory locations in said tag portion of said cache memory; and substituting one of said first set of address signals with a designated signal of said plurality of address lines to logically divide said cache memory into an instruction cache memory and a data cache memory, said designated signal indicating whether an instruction or a datum is accessed.
Claim 4
Dependent Claim
317 words
A structure for configuring a variable sized cache memory addressed by a plurality of address lines, comprising: a data portion of said cache memory, said data portion of said cache memory including a plurality of cache memory locations, said data portion of said cache memory receiving a first set of address signals on a first group of address lines coupled to said plurality of address lines, said first set of address signals specifying a cache memory location in said data portion of said cache memory; a tag portion of said cache memory, said tag portion of said cache memory including a plurality of cache memory locations, said tag portion of said cache memory receiving a second set of address signals on a second group of address lines coupled to said plurality of address lines, said second set of address signals specifying a cache memory location in said tag portion of said cache memory; means for limiting the total number of addressable cache memory locations by setting a first number of address signals in said first set of address signals each to a predetermined logic value to limit said first set of address signals to specify a predetermined number of memory locations in said data portion of said cache memory; means for selecting a line size for said cache memory, said means for selecting a line size setting a second number of address signals in said second set of address signals each to predetermined logic value to limit said second set of address signals to specify a predetermined number of memory locations in said tag portion of said cache memory; and substituting one of said first set of address signals with a designated signal of said plurality of address lines to logically divide said cache memory into an instruction cache memory and a data cache memory, said designated signal indicating whether an instruction or a datum is accessed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-17 | 2000-06-17 | 2000-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-17 | 2004-06-17 | 2004-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-17 | 2008-06-17 | 2008-12-17 | $7700.00 | Window Closed / Lapsed |