Process of fabricating semiconductor device having gate structure doped through diffusion from refractory metal silicide into polysilicon

Claim 1

A process of fabricating first and second field effect transistors opposite in channel conductivity type to each other, comprising the steps of: a) preparing a semiconductor substrate having a first area covered with a first gate insulating layer and a second area covered with a second gate insulating layer and electrically isolated from one another; b) depositing a first layer of intentionally undoped polysilicon over said first and second gate insulating layers by using chemical vapor deposition; c) depositing a second layer of tungsten silicide on said first layer by using sputtering; d) patterning said first and second layers into a first gate structure on said first gate insulating layer and a second gate structure on said second gate insulating layer by using lithographic techniques, said first gate structure having a first strip of said intentionally undoped polysilicon and a second strip of said tungsten silicide, said second gate structure having a third strip of said intentionally undoped polysilicon and a fourth strip of said tungsten silicide; e) covering said second gate structure and said second area with a first photo-resist mask layer by using lithographic techniques; f) implanting a first dopant impurity of one conductivity type into said first area and at least said second strip so as to form first impurity regions in said first area and dope said second strip with said first dopant impurity; g) removing said first photo-resist mask layer; h) covering said first gate structure and said second area with a second photo-resist mask layer by using lithographic techniques; i) implanting a second dopant impurity of the opposite conductivity type to said one conductivity type into said second area and at least said fourth strip so as to form second impurity regions in said second area and dope said fourth strip with said second dopant impurity; j) removing said second photo-resist mask layer; and k) heating said first and second impurity regions and said second and fourth strips to a temperature within a range from 800° C. to 1100° C. so as to concurrently form first source and drain regions from said first impurity regions and second source and drain regions from said second impurity regions and concurrently diffuse said first dopant impurity into said first strip and said second dopant impurity into said third strip.