US5032537A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of doping gate electrodes discretely with either P-type or N-type impurities to form discrete semiconductor regions
Assignee: Hitachi Ltd
•
Filing: 1990-04-16
•
Granted: 1991-07-16
•
Expires: 2010-04-16
Abstract
Abstract The present invention relates to a method of manufacturing a semiconductor device. In a semiconductor substrate formed with a first semiconductor region of P-type and a second semiconductor region of N-type and an insulating film formed between and extending into the first and the second semiconductor regions, gate electrodes of a laminate of a polysilicon layer and a silicide layer are formed on the insulating film covering the first and the second semiconductor regions. A gate electrode situated on the first semiconductor region has an end portion facing and spaced from an end portion of a gate electrode situated on the second semiconductor region. A masking layer is formed on the second semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The first semiconductor region is doped with an impurity of N-type, thereby forming a third semiconductor region in the first semiconductor region. The masking layer is removed from the second semiconductor region and a masking layer is formed on the first semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The second semiconductor region is doped with an impurity of P-type, thereby forming a fourth semiconductor region in the second semiconductor region. By providing a masking layer to fall between the end portions of the gate electrodes, the gate electrodes are discretely doped with either the N-type impurity or the P-type impurity to form discrete semiconductor regions.
Inventors
- 👤 Keiichi Yoshizumi
- 👤 Satoshi Kudo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:20
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D84/0172; H10D84/0177; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10P; H10P14/00; H10P14/40; H10P14/412; H10P14/416; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/071; H10W20/081; H10W20/089; Y; Y10; Y10S; Y10S148/00; Y10S148/106
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
286 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming, on a side of a semiconductor substrate, a first semiconductor region of P-type, a second semiconductor region of N-type in a semiconductor substrate, and a first insulating film between said first and second semiconductor regions; (b) forming a first conductive layer which is made of a laminate film including a polysilicon layer and a silicide layer, which overlies said first semiconductor region and said first insulating film, and which has an end part on said first insulating film; and forming a second conductive layer which is made of a laminate film including a polysilicon layer and a silicide on said substrate, which overlies said second semiconductor region and said first insulating film, and which has an end part on said first insulating film; (c) forming a first mask layer so as to cover at least a part of said second semiconductor region, said first mask layer having an end part between said end parts of said first and second conductive layers which overlie said first insulator film; (d) introducing an impurity of the N-type into said first semiconductor region which is not covered with said first mask layer, thereby to form third semiconductor regions at both end parts of said first conductive layer; (e) forming a second mask layer so as to cover at least a part of said first semiconductor region, said second mask layer having a pattern inverted so that of said first mask layer; and (f) introducing an impurity of P-type into said second semiconductor region which is not covered with said second mask layer, thereby to form fourth semiconductor regions at both end parts of said second conductive layer.
Claim 2
Independent Claim
286 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming, on a side of a semiconductor substrate, a first semiconductor region of P-type, a second semiconductor region of N-type in a semiconductor substrate, and a first insulating film between said first and second semiconductor regions; (b) forming a first conductive layer which is made of a laminate film including a polysilicon layer and a silicide layer, which overlies said first semiconductor region and said first insulating film, and which has an end part on said first insulating film; and forming a second conductive layer which is made of a laminate film including a polysilicon layer and a silicide on said substrate, which overlies said second semiconductor region and said first insulating film, and which has an end part on said first insulating film; (c) forming a first mask layer so as to cover at least a part of said second semiconductor region, said first mask layer having an end part between said end parts of said first and second conductive layers which overlie said first insulator film; (d) introducing an impurity of the N-type into said first semiconductor region which is not covered with said first mask layer, thereby to form third semiconductor regions at both end parts of said first conductive layer; (e) forming a second mask layer so as to cover at least a part of said first semiconductor region, said second mask layer having a pattern inverted so that of said first mask layer; and (f) introducing an impurity of P-type into said second semiconductor region which is not covered with said second mask layer, thereby to form fourth semiconductor regions at both end parts of said second conductive layer.
Claim 3
Dependent Claim
56 words
A method of manufacturing a semiconductor device as defined in claim 1, further comprising the step of: forming a second insulating film on said first and second conductive layers, and then providing holes in said second insulating film so as to bare at least said first and second conductive layers extending to said first insulator film.
Claim 4
Dependent Claim
44 words
A method of manufacturing a semiconductor device as defined in claim 2, wherein in said step of providing said holes in said second insulating film, holes are further provided in said second insulating film so as to bare said third and fourth semiconductor regions.
Claim 5
Dependent Claim
85 words
A method of manufacturing a semiconductor device as defined in claim 3, further comprising the steps of: forming a third mask layer on said second insulating film, said third mask layer having the same pattern as that of said first mask layer; introducing further an impurity of N-type through said holes into parts which are not covered with said third mask layer; and annealing said semiconductor substrate, thereby to form fifth semiconductor regions in said parts into which said N-type impurity has been further introduced.
Claim 6
Independent Claim
256 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming on a semiconductor substrate, a first semiconductor region of P-type, a second semiconductor region of N-type, and a first insulating film extending between and into said first and second semiconductor regions; (b) forming a first conductive layer, comprising a polysilicon layer and a silicide layer, over said first semiconductor region and said first insulating film, and which has an end part on said first insulating film; (c) forming a second conductive layer, comprising a polysilicon layer and a silicide layer, over said second semiconductor region and said first insulating film, and which has an end part on said first insulating film; (d) forming a first mask layer so as to cover at least a part of said second semiconductor region, said first mask layer having an end part between said end parts of said first and second conductive layers which overlie said first insulator film; (e) introducing an impurity of the N-type into said first semiconductor region which is not covered with said first mask layer, thereby to form third semiconductor regions in said first semiconductor region; (f) forming a second mask layer so as to cover at least a part of said first semiconductor region, said second mask layer having a pattern inverted to that of said first mask layer; and (g) introducing an impurity of P-type into said second semiconductor region which is not covered with said second mask layer, thereby to form fourth semiconductor regions in said second semiconductor region.
Claim 7
Independent Claim
256 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming on a semiconductor substrate, a first semiconductor region of P-type, a second semiconductor region of N-type, and a first insulating film extending between and into said first and second semiconductor regions; (b) forming a first conductive layer, comprising a polysilicon layer and a silicide layer, over said first semiconductor region and said first insulating film, and which has an end part on said first insulating film; (c) forming a second conductive layer, comprising a polysilicon layer and a silicide layer, over said second semiconductor region and said first insulating film, and which has an end part on said first insulating film; (d) forming a first mask layer so as to cover at least a part of said second semiconductor region, said first mask layer having an end part between said end parts of said first and second conductive layers which overlie said first insulator film; (e) introducing an impurity of the N-type into said first semiconductor region which is not covered with said first mask layer, thereby to form third semiconductor regions in said first semiconductor region; (f) forming a second mask layer so as to cover at least a part of said first semiconductor region, said second mask layer having a pattern inverted to that of said first mask layer; and (g) introducing an impurity of P-type into said second semiconductor region which is not covered with said second mask layer, thereby to form fourth semiconductor regions in said second semiconductor region.
Claim 8
Dependent Claim
57 words
A method of manufacturing a semiconductor device as defined in claim 5, further comprising the steps of: (h) forming a second insulating film on said first and second conductive layers; and (i) providing holes in said second insulating film so as to bare at least said first and second conductive layers extending to said first insulator film.
Claim 9
Dependent Claim
30 words
A method of manufacturing a semiconductor device as defined in claim 6, wherein said holes are provided in said second insulating film to bare said third and fourth semiconductor regions.
Claim 10
Dependent Claim
43 words
A method of manufacturing a semiconductor device as defined in claim 7, further comprising the step of: (j) forming a further conductive layer on said second insulating film to contact said first and second conductive layers and said third and fourth semiconductor regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-15 | 1995-01-14 | 1995-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-15 | 1999-01-14 | 1999-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-15 | 2003-01-14 | 2003-07-16 | $7700.00 | Window Closed / Lapsed |