Method for the manufacture of cross-couplings between n-channel and p-channel CMOS field effect transistors of static write-read memories

Claim 2

In a method for manufacture of cross-couplings between n-channel and p-channel CMOS field effect transistors of static write-read memories SRAMs wherein buried contacts are provided to diffused n + and p + regions of the n-channel and p-channel transistors in a substrate, and wherein a gate level formed of doped polysilicon and metal silicide is employed as an additional wiring level for said cross-coupling between the n-channel and p-channel transistors, wherein the improvement comprises the steps of: after opening regions for said buried contacts, forming the gate level by deposition of a double layer formed of undoped polysilicon and metal silicide and structuring gate electrodes of the n-channel and p-channel field effect transistors and also structuring the cross-couplings; simultaneously carrying out a doping of cross-coupling regions of said undoped polysilicon and respective gate regions of said undoped polysilicon along with doping of the respective n + and p + drain or source regions in the substrate by masked ion implantation; and subsequently providing a high-temperature treatment of the field effect transistors.

Claim 3

A method according to claim 1 including the step of manufacturing the double layer formed of undoped polysilicon and tantalum disilicide by vapor-deposition.

Claim 4

A method according to claim 1 including the step of manufacturing the double layer formed of undoped polysilicon and tantalum disilicide by sputtering.

Claim 5

A method according to claim 1 including the step of manufacturing the double layer formed of undoped polysilicon and tantalum disilicide by chemical vapor deposition CVD.

Claim 6

A method according to claim 1 including the step of employing the dopants boron and arsenic for the respective ion implantations.

Claim 7

A method according to claim 1 including the step of employing the dopants boron and phosphorous for the respective ion implantations.

Claim 8

A method according to claim 1 including the step of carrying out the temperature treatment in a range from 900° to 950° C. and with a time duration of approximately 60 minutes.

Claim 9

In a method for the manufacture of transistor memory cell arrangements wherein cross-couplings are provided between n-channel and p-channel CMOS field effect transistors of static write-read memories, and wherein an n-doped substrate is provided for the p-channel transducer and a p-doped tub is provided in the n-doped substrate for the n-channel transistor, and wherein contact holes are provided through an insulating layer to the n-doped substrate and the p-doped tub, the improvement comprising the steps of: applying onto the insulating layer a double layer formed of undoped polysilicon and a metal silicide; structuring the double layer to form respective gate electrodes for the p-channel and n-channel transistors and for the cross-coupling; masking the n-channel transistor and part of the cross-coupling, and through ion doping, simultaneously doping the uncovered portion of the cross-coupling and the p-channel gate electrode together with the source or drain region through said opening; removing the mask and masking the p-channel transistor and the doped part of the cross-coupling, and then in another ion implantation step, doping the n-channel gate electrode, the source/drain region of the n-channel transistor through said opening, and uncovered portions of the cross-coupling; removing the mask; and providing a high temperature treatment of the n-channel and p-channel transistors.

Claim 10

In a method for the manufacture of transistor memory cell arrangements wherein cross-couplings are provided between n-channel and p-channel CMOS field effect transistors of static write-read memories, and wherein an n-doped substrate is provided for the p-channel transducer and a p-doped tub is provided in the n-doped substrate for the n-channel transistor, and wherein contact holes are provided through an insulating layer to the n-doped substrate and the p-doped tub, the improvement comprising the steps of: applying onto the insulating layer a double layer formed of undoped polysilicon and a metal silicide; structuring the double layer to form respective gate electrodes for the p-channel and n-channel transistors and for the cross-coupling; masking the n-channel transistor and part of the cross-coupling, and through ion doping, simultaneously doping the uncovered portion of the cross-coupling and the p-channel gate electrode together with the source or drain region through said opening; removing the mask and masking the p-channel transistor and the doped part of the cross-coupling, and then in another ion implantation step, doping the n-channel gate electrode, the source/drain region of the n-channel transistor through said opening, and uncovered portions of the cross-coupling; removing the mask; and providing a high temperature treatment of the n-channel and p-channel transistors.

Claim 11

In a method for the manufacture of transistor memory cell arrangements wherein cross-couplings are provided between n-channel and p-channel CMOS field effect transistors of static write-read memories, and wherein an n-doped substrate is provided for the p-channel transistor and a p-doped tub is provided in the n-doped substrate for the n-channel transistor, and wherein contact holes are provided through an insulating layer to the n-doped substrate and the p-doped tub, the improvement comprising the steps of: applying onto the insulating layer a double layer formed of undoped polysilicon and a metal silicide; structuring the double layer to form respective gate electrodes for the p-channel and n-channel transistors and for the cross-coupling; masking the p-channel transistor and part of the cross-coupling, and through ion doping, simultaneously doping the uncovered portion of the cross-coupling and the n-channel gate electrode together with the source or drain region through said opening; removing the mask and masking the n-channel transistor and the doped part of the cross-coupling, and then in another ion implantation step, doping the p-channel gate electrode, the source/drain region of the p-channel transistor through said opening, and uncovered portions of the cross-coupling; removing the mask; and providing a high temperature treatment of the n-channel and p-channel transistors.

Claim 12

In a method for the manufacture of transistor memory cell arrangements wherein cross-couplings are provided between n-channel and p-channel CMOS field effect transistors of static write-read memories, and wherein an n-doped substrate is provided for the p-channel transistor and a p-doped tub is provided in the n-doped substrate for the n-channel transistor, and wherein contact holes are provided through an insulating layer to the n-doped substrate and the p-doped tub, the improvement comprising the steps of: applying onto the insulating layer a double layer formed of undoped polysilicon and a metal silicide; structuring the double layer to form respective gate electrodes for the p-channel and n-channel transistors and for the cross-coupling; masking the p-channel transistor and part of the cross-coupling, and through ion doping, simultaneously doping the uncovered portion of the cross-coupling and the n-channel gate electrode together with the source or drain region through said opening; removing the mask and masking the n-channel transistor and the doped part of the cross-coupling, and then in another ion implantation step, doping the p-channel gate electrode, the source/drain region of the p-channel transistor through said opening, and uncovered portions of the cross-coupling; removing the mask; and providing a high temperature treatment of the n-channel and p-channel transistors.