Delay circuit using capacitor and transistor

Claim 1

A delay circuit comprising: an input terminal supplied with an input signal; an inverter having an input node connected to said input terminal and an output node; a signal transmission line connected to said output node; a first P-channel metal oxide semiconductor ("MOS") transistor connected to said input terminal; a first N-channel MOS transistor connected to said signal transmission line; a power voltage supply line connected to said first P-channel MOS transistor; a ground voltage supply line operatively connected to said first P-channel MOS transistor; a first capacitor connected to said ground voltage supply line; a first node positioned between said first P-channel MOS transistor and said first capacitor; a second capacitor connected to said ground voltage supply line; a second P-channel MOS transistor having a front gate connected to said input terminal; a second N-channel MOS transistor connected to said signal transmission line, said second N-channel MOS transistor having a front gate; a third N-channel MOS transistor having a front gate connected to said second capacitor: a second node positioned between said second N-channel MOS transistor and said third N-channel MOS transistor and being connected to said front gate of said second N-channel MOS transistor; and a third node positioned between said third N-channel MOS transistor and said second capacitor; said first P-channel MOS transistor forming a first source-drain current path between said power voltage supply line and said first node, said first P-channel MOS transistor including a front gate connected to said input terminal, said first N-channel MOS transistor forming a second source-drain current path between said signal transmission line and said first node, and said first N-channel MOS transistor including a front gate connected to said first node, said second P-channel MOS transistor forming a third source-drain current path between said power voltage supply line and said third node, said second N-channel MOS transistor forming a fourth source-drain current path between said signal transmission line and said second node, and said third N-channel MOS transistor forming a fifth source-drain current path between said second node and said third node.