US4644182A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay circuit having delay time period determined by discharging operation
Assignee: Fujitsu Ltd
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Filing: 1985-11-08
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Granted: 1987-02-17
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Expires: 2005-11-08
Abstract
Abstract A delay circuit including: a P-channel enhancement-type transistor (Q 11 ), linked between an input terminal (IN) and an output terminal (OUT); a capacitor (C) connected to the gate of the transistor (Q 11 ); a charging switch (SW 1 ) for charging the capacitor (C); a discharging switch (SW 2 ) for discharging the capacitor (C); and a control circuit (CONT) for controlling the charging switch (SW 1 ) and the discharging switch (SW 2 ). The delay time period is determined by the discharging operation of the discharging switch (SW 1 ) after the charging operation of the charging switch (SW 1 ).
Inventors
- 👤 Hiromi Kawashima
- 👤 Hideki Arakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:01
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/145; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C16/32
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
172 words
A delay circuit comprising: an input terminal means (IN); an output terminal means (OUT); a power supply means (GND); a transistor (Q 11 ) having a gate, a source and a drain, said source and drain being connected between said input terminal means (IN) and said output terminal means (OUT); a capacitor (C), connected between the gate of said transistor (Q 11 ) and said power supply means (GND); a charging switch (SW 1 ), connected between said input terminal means (IN) and the gate of said transistor (Q 11 ), for charging said capacitor (C); a discharging switch (SW 2 ), connected to the gate of said transistor (Q 11 ), for discharging said capacitor (C); a constant current source (CS), connected between said discharging switch (SW 2 ) and said power supply means (GND); and control means (CONT), connected to said charging switch (SW 1 ) and to said discharging switch (SW 2 ), for complementarily controlling said charging switch (SW 1 ) and said discharging switch (SW 2 ).
Claim 2
Dependent Claim
172 words
A delay circuit comprising: an input terminal means (IN); an output terminal means (OUT); a power supply means (GND); a transistor (Q 11 ) having a gate, a source and a drain, said source and drain being connected between said input terminal means (IN) and said output terminal means (OUT); a capacitor (C), connected between the gate of said transistor (Q 11 ) and said power supply means (GND); a charging switch (SW 1 ), connected between said input terminal means (IN) and the gate of said transistor (Q 11 ), for charging said capacitor (C); a discharging switch (SW 2 ), connected to the gate of said transistor (Q 11 ), for discharging said capacitor (C); a constant current source (CS), connected between said discharging switch (SW 2 ) and said power supply means (GND); and control means (CONT), connected to said charging switch (SW 1 ) and to said discharging switch (SW 2 ), for complementarily controlling said charging switch (SW 1 ) and said discharging switch (SW 2 ).
Claim 3
Dependent Claim
34 words
A circuit as set forth in claim 1, wherein said transistor (Q 11 ) is of a P-channel type, and said charging switch (SW 1 ) comprises an N-channel enhancement-type transistor (Q 12 ).
Claim 4
Dependent Claim
23 words
A circuit as set forth in claim 1, wherein said discharging switch (SW 2 ) comprises a P-channel enhancement-type transistor (Q 13 ).
Claim 5
Dependent Claim
27 words
A circuit as set forth in claim 1, wherein said constant current source (CS) comprises an N-channel depletion-type transistor having a source connected to the gate thereof.
Claim 6
Dependent Claim
83 words
A circuit as set forth in claim 1, wherein said control means (CONT) turns on said charging switch (SW 1 ) and turns off said discharging switch (SW 2 ) when the potential at said input terminal means (IN) is lower than a predetermined value, and said control means (CONT) turns off said charging switch (SW 1 ) and turns on said discharging switch (SW 2 ) when the potential at said input terminal means (IN) is not lower than said predetermined value.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-16 | 1990-08-18 | 1991-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-16 | 1994-08-18 | 1995-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-16 | 1998-08-18 | 1999-02-17 | $7700.00 | Window Closed / Lapsed |