US3740581A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Precision switching circuit for analog signals
Assignee: Raytheon Co
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Filing: 1972-03-08
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Granted: 1973-06-19
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Expires: 1992-03-08
Abstract
Abstract A precision high-speed, low impedance switching circuit is disclosed which is suitable for use with video or other high frequency analog signals. A J-FET is used as the switching element but is controlled by means of a novel circuit which minimizes channel impedance modulation effects. The gate of the J-FET is connected to the output of a control transistor, the input of the control transistor being connected to the input signal, thereby allowing the effective parasitic input capacity at the gate of the J-FET switch to be charged and discharged in accordance with the fluctuations of the input signal.
Inventors
- 👤 H Pfiffner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:50
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/567; H03K17/687; H03K17/6877
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
105 words
A precision high-speed, low-impedance circuit for switching an analog signal, said circuit comprising: a J-FET switching element having an input electrode, an output electrode and a gate electrode; a control transistor having an input electrode connected to said J-FET switching element input electrode, an output electrode connected to said J-FET switching element gate electrode, and a control electrode; means for providing a unidirectional low impedance path between said J-FET gate electrode and said control transistor control electrode; and switching means for simultaneously applying an ''''off'''' control voltage to said control transistor control electrode and via said unidirectional low impedance path to said J-FET gate electrode.
Claim 2
Dependent Claim
105 words
A precision high-speed, low-impedance circuit for switching an analog signal, said circuit comprising: a J-FET switching element having an input electrode, an output electrode and a gate electrode; a control transistor having an input electrode connected to said J-FET switching element input electrode, an output electrode connected to said J-FET switching element gate electrode, and a control electrode; means for providing a unidirectional low impedance path between said J-FET gate electrode and said control transistor control electrode; and switching means for simultaneously applying an ''''off'''' control voltage to said control transistor control electrode and via said unidirectional low impedance path to said J-FET gate electrode.
Claim 3
Dependent Claim
30 words
The circuit of claim 1 wherein said control transistor is a bipolar device having collector, emitter, and base electrodes functioning respectively as said control transistor input, output and control electrodes.
Claim 4
Dependent Claim
38 words
The circuit of claim 1 wherein said control transistor is a MOS-FET device and said control electrode is the insulated gate of said MOS-FET device, whereby complete isolation is provided between said control voltage and said signal voltage.
Claim 5
Dependent Claim
25 words
The circuit of claim 1 wherein said control transistor is a J-FET device and said control electrode is the gate electrode of said J-FET device.
Claim 6
Dependent Claim
16 words
The circuit of claim 4 further comprising a bias potential in series with said unidirectional path.
References Cited (Backward Citations)
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US3596109A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-18 | 1976-12-18 | 1977-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-18 | 1980-12-18 | 1981-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-18 | 1984-12-18 | 1985-06-19 | $7700.00 | Window Closed / Lapsed |