Delay circuit and latch circuit for controlling setup time and hold time of pulse signals

Claim 1

A semiconductor device generating an output signal having a programmable setup time and hold time which can be matched to a setup time and hold time of an adjacent device coupled to the semiconductor device, the semiconductor device receiving a data pulse signal, comprising: a plurality of series circuits connected in parallel, wherein each of said series circuits is composed of a capacitor and a switching element having an open position and a closed position determined in response to a control signal, said plurality of series circuits receiving the data pulse signal and delaying a pulse of said pulse signal by a time period defined by the number of series circuits having a switching element in the closed position, a delayed pulse being output from the plurality of series circuits; and means receiving a clock signal and the delayed pulse for latching the delayed pulse during an active transition of the clock signal, the latch generating an output signal based upon a logic level of the latched pulse, wherein the hold time portion of the received delayed pulse increases and the setup time portion of the received pulse decreases as the delay time period increases.