US5012143A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated delay line
Assignee: Trident Microsystems Far East Ltd Cayman Islands
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Filing: 1989-10-04
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Granted: 1991-04-30
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Expires: 2009-10-04
Abstract
Abstract A delay line, especially for delaying t.v. signals, includes a series of signal storage capacitances, an input line, an output line, selection transistors between the storage capacitances and the input and output lines and a digital shift register for activating the selection transistors. According to the invention, the output line comprises a central part, on either side of which signal storage capacitances with associated selection transistors are located, which in turn are located between the central part of the output line and the associated parts of the shift register. The design according to the invention results in a compact configuration, which has the advantage that the parasitic capacitance of the output line is comparatively low. The configuration can be readily extended to two interlaced delay lines having a single common shift register.
Inventors
- 👤 Arnoldus J. J. Boudewijns
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:51
CPC Classifications
G; G11; G11C; G11C7/00; G11C27/00; G11C27/04; G11C19/00; G11C19/18; G11C19/182; G11C19/184
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
208 words
An integrated circuit having a delay line arranged at a surface of a semiconductor body and comprising a series of signal storage capacitances, an input line for supplying signals and a read-out line for reading out the stored signals, a plurality of pairs of transistors, which are each coupled to a signal storage capacitance and of which a transistor, designated the read-in transistor, comprises a switch between the capacitance and the read-in line, while the other transistor, designated the read-out transistor, comprises a switch between the capacitance and the read-out line, and further comprising a digital shift register having a plurality of outputs which are connected to control electrodes of the transistors, characterized in that the delay line comprises at least two adjacent parts with a common centrally-arranged part of the read-out line therebetween, the signal storage capacitances and the associated pairs of transistors and parts of the shift register being located on both sides of said parts of the read-out line in such a manner that on both sides of said part of the read-out line the signal storage capacitances with their coupled transistors of one of the parts of the delay line are located between the read-out line and the associated part of the shift register.
Claim 2
Dependent Claim
208 words
An integrated circuit having a delay line arranged at a surface of a semiconductor body and comprising a series of signal storage capacitances, an input line for supplying signals and a read-out line for reading out the stored signals, a plurality of pairs of transistors, which are each coupled to a signal storage capacitance and of which a transistor, designated the read-in transistor, comprises a switch between the capacitance and the read-in line, while the other transistor, designated the read-out transistor, comprises a switch between the capacitance and the read-out line, and further comprising a digital shift register having a plurality of outputs which are connected to control electrodes of the transistors, characterized in that the delay line comprises at least two adjacent parts with a common centrally-arranged part of the read-out line therebetween, the signal storage capacitances and the associated pairs of transistors and parts of the shift register being located on both sides of said parts of the read-out line in such a manner that on both sides of said part of the read-out line the signal storage capacitances with their coupled transistors of one of the parts of the delay line are located between the read-out line and the associated part of the shift register.
Claim 3
Dependent Claim
42 words
An integrated circuit as claimed in claim 1, characterized in that two read-out transistors located on both sides of the centrally arranged part of the read-out line are connected by a common contact to the centrally arranged part of the read-out line.
Claim 4
Dependent Claim
63 words
An integrated circuit as claimed in claim 1, further comprising a second delay line, whose construction is analogous to that of the first delay line and which also comprises at least two parts, which are arranged on either side of the two parts of the first delay line, said parts of the shift register being common to the first and second delay lines.
Claim 5
Dependent Claim
63 words
An integrated circuit as claimed in claim 2, further comprises a second delay line, whose construction is analogous to that of the first delay line and which also comprises at least two parts, which are arranged on either side of the two parts of the first delay line, said parts of the shift register being common to the first and second delay lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |