US5764083A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pipelined clock distribution for self resetting CMOS circuits
Assignee: International Business Machines Corp
•
Filing: 1996-06-10
•
Granted: 1998-06-09
•
Expires: 2016-06-10
Abstract
Abstract A system for clocking self resetting CMOS (SRCMOS) circuits operating at high speed includes a clock generator circuit which produces a first pipeline clock pulse of relatively narrow width from a leading edge of a system clock having a relatively long duration with respect to the first pipeline clock, a number of delay circuits, the time duration of each of the delay circuits being determined by characteristics of evaluation logic in the SRCMOS circuits being clocked, the delay circuits being connected in a serial pipeline fashion such that each subsequent delayed clock pulse overlaps a preceding clock pulse by at least a predetermined minimum time duration. The clocking system also includes a cycle relax mode whereby the clock pulse output of the clock generator circuit may be extended for test or diagnostic purposes.
Inventors
- 👤 Bang T. Nguyen
- 👤 Mark Daniel Papermaster
- 👤 Giao Ngoc Pham
- 👤 Trang Khanh Ta
- 👤 Willem Bernard van der Hoeven
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:45
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/15026
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
126 words
A system for clocking logic circuits operating at high speed, comprising: a clock generator circuit for generating a first clock pulse of relatively narrow width from a leading edge of a system clock having a relatively long duration with respect to the first clock pulse; and a plurality of delay circuits, the delay time of each of the delay circuits being determined by characteristics of evaluation logic in the logic circuits being clocked, the delay circuits being connected in series such that each subsequent delayed clock pulse overlaps a preceding clock pulse by at least a predetermined minimum time duration, each delay circuit producing a clock signal at a time in each system clock cycle appropriate for evaluation of a predetermined stage of the logic circuit.
Claim 2
Independent Claim
126 words
A system for clocking logic circuits operating at high speed, comprising: a clock generator circuit for generating a first clock pulse of relatively narrow width from a leading edge of a system clock having a relatively long duration with respect to the first clock pulse; and a plurality of delay circuits, the delay time of each of the delay circuits being determined by characteristics of evaluation logic in the logic circuits being clocked, the delay circuits being connected in series such that each subsequent delayed clock pulse overlaps a preceding clock pulse by at least a predetermined minimum time duration, each delay circuit producing a clock signal at a time in each system clock cycle appropriate for evaluation of a predetermined stage of the logic circuit.
Claim 3
Dependent Claim
45 words
A system for clocking logic circuits operating at high speed, according to claim 1, wherein the clock generator circuit further comprises: a cycle relax control circuit which controls the duration of the clock pulse output of the clock generator circuit for test or diagnostic purposes.
Claim 4
Dependent Claim
27 words
A system for clocking logic circuits operating at high speed, according to claim 1, wherein the logic circuit comprises: one or more self resetting CMOS logic circuits.
Claim 5
Dependent Claim
35 words
A system for clocking logic circuits operating at high speed, according to claim 1, wherein each of the delay circuits comprises: one or more logic blocks, each having a predetermined input to output delay characteristic.
Claim 6
Dependent Claim
24 words
A system for clocking logic circuits operating at high speed, according to claim 1, wherein each of the logic blocks is an inverter circuit.
Claim 7
Dependent Claim
56 words
A logic unit for use in an information handling system, comprising: a set of sequentially evaluated logic blocks, operable at a high clock speed; a differential clock pipeline circuit for generating clock pulses of appropriate time duration and position for evaluation of the logic blocks; and wherein each logic block is a self resetting CMOS circuit.
Claim 8
Dependent Claim
56 words
A logic unit for use in an information handling system, comprising: a set of sequentially evaluated logic blocks, operable at a high clock speed; a differential clock pipeline circuit for generating clock pulses of appropriate time duration and position for evaluation of the logic blocks; and wherein each logic block is a self resetting CMOS circuit.
Claim 9
Dependent Claim
168 words
A logic unit for use in an information handling system, comprising: a set of sequentially evaluated logic blocks, operable at a high clock speed; a differential clock pipline circuit for generating clock pulses of appropriate time duration and position for evaluation of the logic blocks; and wherein the differential clock pipeline circuit comprises: a clock generator circuit for generating a first clock pulse of relatively narrow width from a leading edge of a system clock having a relatively long duration with respect to the first clock pulse; and a plurality of delay circuits, the delay time of each of the delay circuits being determined by characteristics of evaluation logic in the logic circuits being clocked, the delay circuits being connected in series such that each subsequent delayed clock pulse overlaps a preceding clock pulse by at least a predetermined minimum time duration, each delay circuit producing a clock signal at a time in each system clock cycle appropriate for evaluation of a predetermined stage of the logic circuit.
Claim 10
Dependent Claim
168 words
A logic unit for use in an information handling system, comprising: a set of sequentially evaluated logic blocks, operable at a high clock speed; a differential clock pipline circuit for generating clock pulses of appropriate time duration and position for evaluation of the logic blocks; and wherein the differential clock pipeline circuit comprises: a clock generator circuit for generating a first clock pulse of relatively narrow width from a leading edge of a system clock having a relatively long duration with respect to the first clock pulse; and a plurality of delay circuits, the delay time of each of the delay circuits being determined by characteristics of evaluation logic in the logic circuits being clocked, the delay circuits being connected in series such that each subsequent delayed clock pulse overlaps a preceding clock pulse by at least a predetermined minimum time duration, each delay circuit producing a clock signal at a time in each system clock cycle appropriate for evaluation of a predetermined stage of the logic circuit.
Claim 11
Dependent Claim
46 words
A logic unit for use in an information handling system, according to claim 7, wherein the differential clock pipeline circuit further comprises: a cycle relax control circuit which controls the duration of the clock pulse output of the clock generator circuit for test or diagnostic purposes.
Claim 12
Independent Claim
104 words
A method for clocking logic circuits operating at high speed, comprising the steps of: generating a first clock pulse having a relatively short duration from a leading edge of a system clock pulse having a relatively long duration with respect to the first clock pulse; and delaying the first clock pulse in a plurality of delay circuits, the delay time of each of the delay circuits being determined by characteristics of evaluation logic in logic circuits being clocked, each delay circuit producing a clock signal at a time in each system clock cycle appropriate for evaluation of a predetermined stage of the logic circuit.
Claim 13
Independent Claim
104 words
A method for clocking logic circuits operating at high speed, comprising the steps of: generating a first clock pulse having a relatively short duration from a leading edge of a system clock pulse having a relatively long duration with respect to the first clock pulse; and delaying the first clock pulse in a plurality of delay circuits, the delay time of each of the delay circuits being determined by characteristics of evaluation logic in logic circuits being clocked, each delay circuit producing a clock signal at a time in each system clock cycle appropriate for evaluation of a predetermined stage of the logic circuit.
Claim 14
Dependent Claim
42 words
A method for clocking logic circuits operating at high speed, according to claim 9, wherein the delay circuits are connected in series such that each subsequent delayed clock pulse overlaps a preceding clock pulse by at least a predetermined minimum time duration.
Claim 15
Dependent Claim
41 words
A method for clocking logic circuits operating at high speed, according to claim 9, further comprising the step of: controlling the duration of the clock pulse output of the clock generator circuit, in a cycle relaxation control circuit, for diagnostic purposes.
Claim 16
Dependent Claim
50 words
A method for clocking logic circuits operating at high speed, according to claim 9, wherein the delaying step further comprises the steps of: generating a series of delayed pulses from the first clock pulse, wherein each of the delayed pulses is output from one of a plurality of delay circuits.
References Cited (Backward Citations)
US3829790A
Cited
US4414637A
Cited
US4862096A
Cited
US5258660A
Cited
US5173618A
Cited
US5208776A
Cited
US5216301A
Cited
US5389831A
Cited
US5532625A
Cited
US5517136A
Cited
US5614845A
Cited
US5638008A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-08 | 2001-12-08 | 2002-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-08 | 2005-12-08 | 2006-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-08 | 2009-12-08 | 2010-06-09 | $7700.00 | Window Closed / Lapsed |