Method and apparatus for generating an asynchronously clocked signal in a synchronously clocked programmable device

Claim 2

In a programmable device having synchronously clocked registers, a method for generating an asynchronously clocked signal without employing said synchronously clocked registers, said method comprising: receiving an input signal; receiving an event signal; generating an intermediate signal, said intermediate signal having a same signal state as said input signal when said event signal is in a first signal state, said intermediate signal remaining in said same signal state when said event signal is in a second signal state; and producing said asynchronously clocked signal when said intermediate signal is in said same signal state and said event signal transitions from said first signal state to said second signal state, said asynchronously clocked signal remaining unchanged when said event signal transitions from said second signal state to said first signal state.

Claim 3

The method of claim 1 wherein said transition edge of said event signal is a rising edge.

Claim 4

The method of claim 1 wherein said transition edge of said event signal is a falling edge.

Claim 5

The method of claim 1 wherein said event signal is generated within said synchronously clocked programmable device.

Claim 6

The method of claim 1 wherein said event signal is generated from a plurality of product terms.

Claim 7

The method of claim 1 wherein said event signal is generated from one product term.

Claim 8

The method of claim 1 wherein said input signal is generated within said synchronously clocked programmable device.

Claim 9

The method of claim 1 wherein said input signal is generated from a plurality of product terms.

Claim 10

The method of claim 1 wherein said programmable device includes a plurality of AND gates coupled to a plurality of OR gates.

Claim 11

The method of claim 1 wherein said programmable device includes a first plurality of NOR gates coupled to a second plurality of NOR gates.

Claim 12

In a programmable device having synchronously clocked registers, a method for generating an asynchronously clocked signal without employing said synchronously clocked registers, said method comprising: receiving an input signal; receiving an event signal; generating a first polarity signal at a first node when said event signal is in a first logic state, said first polarity signal remaining unchanged when said event signal is in a second logic state; generating said asynchronously clocked signal at a second node in response to a first transition edge of said event signal, said asynchronously clocked signal having a same polarity as said first polarity signal at said first node, said asynchronously clocked signal remaining unchanged in response to a second transition edge of said event signal.

Claim 13

In a programmable device having synchronously clocked registers, a method for generating an asynchronously clocked signal without employing said synchronously clocked registers, said method comprising: receiving an input signal; receiving an event signal; generating a first polarity signal at a first node when said event signal is in a first logic state, said first polarity signal remaining unchanged when said event signal is in a second logic state; generating said asynchronously clocked signal at a second node in response to a first transition edge of said event signal, said asynchronously clocked signal having a same polarity as said first polarity signal at said first node, said asynchronously clocked signal remaining unchanged in response to a second transition edge of said event signal.

Claim 14

In a programmable device having synchronously clocked registers, a circuit for generating an asynchronously clocked signal without employing said synchronously clocked registers, said circuit comprising: first circuitry operable to receive an input signal and an event signal, said first circuitry generating an intermediate signal having a same signal state as said input signal when said event signal is in a first signal state, said intermediate signal remaining in said same signal state when said event signal is in a second signal state; second circuitry coupled to said first circuitry and said event signal, said second circuitry operable to receive said intermediate signal, said second circuitry providing said asynchronously clocked signal from said intermediate signal in response to a transition edge of said event signal.

Claim 15

In a programmable device having synchronously clocked registers, a circuit for generating an asynchronously clocked signal without employing said synchronously clocked registers, said circuit comprising: first circuitry operable to receive an input signal and an event signal, said first circuitry generating an intermediate signal having a same signal state as said input signal when said event signal is in a first signal state, said intermediate signal remaining in said same signal state when said event signal is in a second signal state; second circuitry coupled to said first circuitry and said event signal, said second circuitry operable to receive said intermediate signal, said second circuitry providing said asynchronously clocked signal from said intermediate signal in response to a transition edge of said event signal.

Claim 16

The circuit of claim 12 wherein said second circuitry provides said asynchronously clocked signal when said intermediate signal is in said same signal state and said event signal transitions from said first signal state to said second signal state, said asynchronously clocked signal remaining unchanged when said event signal transitions from said second signal state to said first signal state.

Claim 17

The circuit of claim 12 wherein said transition edge of said event signal is a rising edge.

Claim 18

The circuit of claim 12 wherein said transition edge of said event signal is a falling edge.

Claim 19

The circuit of claim 12 wherein said event signal is generated within said synchronously clocked programmable device.

Claim 20

The circuit of claim 12 wherein said event signal is generated from a plurality of product terms.

Claim 21

The circuit of claim 12 wherein said event signal is generated from one product term.

Claim 22

The circuit of claim 12 wherein said input signal is generated within said synchronously clocked programmable device.

Claim 23

The circuit of claim 12 wherein said input signal is generated from a plurality of product terms.

Claim 24

A programmable logic device comprising: at least one input; at least one clock input; a product term array for generating at least one AND term, said product term array having a first plurality of combinatorial logic gates, said product term array coupled to said at least one input; a product term allocator for receiving said at least one AND term from said product term array, said product term allocator having a second plurality of combinatorial logic gates, said product term allocator coupled to said product term array; and at least one macrocell having at least one register synchronously clocked by a clock signal received from said at least one clock input, said at least one macrocell coupled to said product term allocator and at least one output; wherein said first plurality of combinatorial logic gates of said product term is coupled to said second plurality of combinatorial logic gates of said product term allocator such that a signal provided to said product term array is asynchronously clocked through said programmable logic device without utilizing said at least one register synchronously clocked by said clock signal.

Claim 25

A programmable logic device comprising: at least one input; at least one clock input; a product term array for generating at least one AND term, said product term array having a first plurality of combinatorial logic gates, said product term array coupled to said at least one input; a product term allocator for receiving said at least one AND term from said product term array, said product term allocator having a second plurality of combinatorial logic gates, said product term allocator coupled to said product term array; and at least one macrocell having at least one register synchronously clocked by a clock signal received from said at least one clock input, said at least one macrocell coupled to said product term allocator and at least one output; wherein said first plurality of combinatorial logic gates of said product term is coupled to said second plurality of combinatorial logic gates of said product term allocator such that a signal provided to said product term array is asynchronously clocked through said programmable logic device without utilizing said at least one register synchronously clocked by said clock signal.

Claim 26

In a programmable logic device, having no hardware capability to generate an asynchronously clocked signal without utilizing a register element, a method for programming the programmable logic device to generate an asynchronously clocked signal comprising: receiving an input signal; receiving an event signal; generating an intermediate signal, said intermediate signal having a same signal state as said input signal when said event signal is in a first signal state, said intermediate signal remaining in said same signal state when said event signal is in a second signal state; and producing said asynchronously clocked signal when said intermediate signal is in said same signal state and said event signal transitions from said first signal state to said second signal state, said asynchronously clocked signal remaining unchanged when said event signal transitions from said second signal state to said first signal state.

Claim 27

In a programmable logic device, having no hardware capability to generate an asynchronously clocked signal without utilizing a register element, a method for programming the programmable logic device to generate an asynchronously clocked signal comprising: receiving an input signal; receiving an event signal; generating an intermediate signal, said intermediate signal having a same signal state as said input signal when said event signal is in a first signal state, said intermediate signal remaining in said same signal state when said event signal is in a second signal state; and producing said asynchronously clocked signal when said intermediate signal is in said same signal state and said event signal transitions from said first signal state to said second signal state, said asynchronously clocked signal remaining unchanged when said event signal transitions from said second signal state to said first signal state.