Programmable multiphase sequence controller

Claim 2

A sequence controller comprising: means for generating a system clock signal of period p; means responsive to said system clock signal for generating a plurality of n periodic time slice signals, each time slice signal having a similar period P proportional to the product of n and p according to an integer constant of proportionality, phase relationships between said time slice signals being such that each said time slice signal is of a phase differing from phases of the other time slice signals; means for selecting first and second time slice signals from among said n time slice signals; and means for periodically generating an output pulse having a rising edge timed according to said first time slice clock signal and having a falling edge timed according to said second time slice clock signal.

Claim 3

The sequence controller in accordance with claim 1 wherein said integer constant of proportionality is adjustable.

Claim 4

The sequence controller in accordance with claim 1 wherein the magnitude of n is adjustable.

Claim 5

The sequence controller in accordance with claim 1 wherein said integer constant of proportionality is adjustable and wherein the magnitude of n is adjustable.

Claim 6

A sequence controller comprising: means for generating a periodic system clock signal; means for maintaining a count of periods of said system clock signal and for resetting said count to an initial value when said count reaches a predetermined count limit; means for generating a plurality of time slice signals, each time slice signal corresponding to a separate magnitude of said count, each time slice signal being of a first state when said count has the corresponding magnitude and of a second state when said count does not have the corresponding magnitude; means for selecting first and second time slice signals from among said plurality of time slice signals; and means for periodically generating an output pulse having a rising edge timed according to said selected first one of said time slice signals and having a falling edge timed according to said selected second one of said time slice signals.

Claim 7

A sequence controller comprising: means for generating a periodic system clock signal; means for maintaining a count of periods of said system clock signal and for resetting said count to an initial value when said count reaches a predetermined count limit; means for generating a plurality of time slice signals, each time slice signal corresponding to a separate magnitude of said count, each time slice signal being of a first state when said count has the corresponding magnitude and of a second state when said count does not have the corresponding magnitude; means for selecting first and second time slice signals from among said plurality of time slice signals; and means for periodically generating an output pulse having a rising edge timed according to said selected first one of said time slice signals and having a falling edge timed according to said selected second one of said time slice signals.

Claim 8

A sequence controller comprising: means for generating a periodic system clock signal; means responsive to said system clock signal for producing a periodic output clock signal of period an adjustable integer multiple of the period of said system clock signal; means for maintaining a count of periods of said output clock signal, for resetting said count to an initial value when said count reaches a predetermined count limit, and for producing an encoded output signal representing the magnitude of said count; means for decoding said encoded output signal thereby generating a plurality of time slice signals, each time slice signal corresponding to a separate magnitude of said count, each time slice signal being of a first state when said count has the corresponding magnitude and of a second state when said count does not have the corresponding magnitude; means for selecting first and second time slice signals from among said plurality of time slice signals; and means for periodically generating an output pulse having a rising edge timed according to said selected first time slice signal and having a falling edge timed according to said selected second time slice signal.

Claim 9

A sequence controller comprising: means for generating a periodic system clock signal; means responsive to said system clock signal for producing a periodic output clock signal of period an adjustable integer multiple of the period of said system clock signal; means for maintaining a count of periods of said output clock signal, for resetting said count to an initial value when said count reaches a predetermined count limit, and for producing an encoded output signal representing the magnitude of said count; means for decoding said encoded output signal thereby generating a plurality of time slice signals, each time slice signal corresponding to a separate magnitude of said count, each time slice signal being of a first state when said count has the corresponding magnitude and of a second state when said count does not have the corresponding magnitude; means for selecting first and second time slice signals from among said plurality of time slice signals; and means for periodically generating an output pulse having a rising edge timed according to said selected first time slice signal and having a falling edge timed according to said selected second time slice signal.

Claim 10

A sequence controller comprising: a plurality of time slice means each periodically producing an adjustable number of sequentially asserted time slice signals; and a plurality of phase generator means, at least one phase generator means corresponding to each of said time slice means, each phase generator means having as input the time slice signals produced by its corresponding time slice means, each phase generator means producing a square wave output signal, the timing of the rising and falling edges of each pulse thereof being determined by a selectable pair of its input time slice signals.

Claim 11

A sequence controller comprising: a plurality of time slice means each periodically producing an adjustable number of sequentially asserted time slice signals; and a plurality of phase generator means, at least one phase generator means corresponding to each of said time slice means, each phase generator means having as input the time slice signals produced by its corresponding time slice means, each phase generator means producing a square wave output signal, the timing of the rising and falling edges of each pulse thereof being determined by a selectable pair of its input time slice signals.

Claim 12

The sequence controller according to claim 7 further comprising means for transmitting an enable signal to at least one of said plurality of time slice means in response to assertion of particular time slice signals produced by said plurality of time slice means, said at least one time slice means producing time slice signals only when output enabled by said enable signal.

Claim 13

A sequence controller comprising: means for generating a periodic system clock signal; a plurality of time slice means each comprising means responsive to said system clock signal for producing a periodic output clock signal of period an adjustable integer multiple of the period of said system clock signal, for maintaining a count of periods of said output clock signal, for resetting said count to an initial value when said count reaches a predetermined count limit, for producing an encoded signal representing the magnitude of said count, for decoding said encoded signal when output enabled by an input enable signal thereby generating a plurality of time slice signals, each time slice signal corresponding to a separate magnitude of said count, each time slice signal being of a first state when said count has the corresponding magnitude and of a second state when said count does not have the corresponding magnitude; a plurality of phase generator means, each receiving as input the time slice signals produced by a separate one of said time slice means, each phase generator means periodically generating an output pulse having a rising edge timed according to a selected first one of its input time slice signals and having a falling edge timed according to a selected second one of its input time slice signals; and means for transmitting a separate enable PG,19 signal to each of said time slice means, each enable signal being of state determined according to the state of at least one of said time slice signals produced by said plurality of time slice means.

Claim 14

A sequence controller comprising: means for generating a periodic system clock signal; a plurality of time slice means each comprising means responsive to said system clock signal for producing a periodic output clock signal of period an adjustable integer multiple of the period of said system clock signal, for maintaining a count of periods of said output clock signal, for resetting said count to an initial value when said count reaches a predetermined count limit, for producing an encoded signal representing the magnitude of said count, for decoding said encoded signal when output enabled by an input enable signal thereby generating a plurality of time slice signals, each time slice signal corresponding to a separate magnitude of said count, each time slice signal being of a first state when said count has the corresponding magnitude and of a second state when said count does not have the corresponding magnitude; a plurality of phase generator means, each receiving as input the time slice signals produced by a separate one of said time slice means, each phase generator means periodically generating an output pulse having a rising edge timed according to a selected first one of its input time slice signals and having a falling edge timed according to a selected second one of its input time slice signals; and means for transmitting a separate enable PG,19 signal to each of said time slice means, each enable signal being of state determined according to the state of at least one of said time slice signals produced by said plurality of time slice means.