US3829790A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock distribution circuit
Assignee: AG Communication Systems Corp
•
Filing: 1973-09-14
•
Granted: 1974-08-13
•
Expires: 1993-09-14
Abstract
Abstract A clock distribution circuit that generates consecutive timing pulses of a first predetermined time duration on a first plurality of output lines and a corresponding number of timing pulses of a second predetermined duration that is less than the first time duration on a second plurality of output lines. The leading edge of every timing pulse of the second time duration is nearly coincident with the leading edge of a corresponding timing pulse of the first predetermined duration. To generate the two sets of timing pulses, the clock circuit is provided with a crystal controlled oscillator, a phase feedback stage, a dual rank shift register, delay gating, feedback gating and feed forward gating arrangements.
Inventors
- 👤 M Macrander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:23
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; Y; Y10; Y10S; Y10S331/00; Y10S331/03
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
216 words
A clock distribution circuit for generating a first plurality of consecutive timing pulse outputs, each of a first predetermined time duration and a second plurality of sequential timing pulse outputs, each of a second predetermined time duration that is shorter than said first predetermined time duration with the leading edge of each timing pulse of said first and second plurality of outputs occuring nearly coincident in time, comprising: oscillator means for generating drive signals, said oscillator means operating at a predetermined frequency; phase feedback circuity means for providing two mutually exclusive outputs at a frequency related to said oscillator frequency, said phase feedback circuity means being driven by said oscillator means; shift register means driven by said two mutually exclusive outputs for providing a sequential train of data pulses at a plurality of outputs; feed forward and feedback gating means, FFGM, connected to said data pulse outputs for generating said first and second plurality of timing pulse outputs; and delay gating means connected to said phase feedback circuity means and said FFGM for providing a delay signal to said FFGM, said delayed signal being combined with said train of data pulse outputs of said shift register means to generate said first plurality of consecutive timing pulse outputs and said second plurality of sequential timing pulse outputs.
Claim 2
Dependent Claim
216 words
A clock distribution circuit for generating a first plurality of consecutive timing pulse outputs, each of a first predetermined time duration and a second plurality of sequential timing pulse outputs, each of a second predetermined time duration that is shorter than said first predetermined time duration with the leading edge of each timing pulse of said first and second plurality of outputs occuring nearly coincident in time, comprising: oscillator means for generating drive signals, said oscillator means operating at a predetermined frequency; phase feedback circuity means for providing two mutually exclusive outputs at a frequency related to said oscillator frequency, said phase feedback circuity means being driven by said oscillator means; shift register means driven by said two mutually exclusive outputs for providing a sequential train of data pulses at a plurality of outputs; feed forward and feedback gating means, FFGM, connected to said data pulse outputs for generating said first and second plurality of timing pulse outputs; and delay gating means connected to said phase feedback circuity means and said FFGM for providing a delay signal to said FFGM, said delayed signal being combined with said train of data pulse outputs of said shift register means to generate said first plurality of consecutive timing pulse outputs and said second plurality of sequential timing pulse outputs.
Claim 3
Dependent Claim
109 words
A clock distribution circuit as recited in claim 1 wherein said first plurality of consecutive timing pulse outputs and said second plurality of sequential timing pulse outputs each include N pulses, wherein N is an integer greater than 1. and wherein said FFGM and said shift register means each include N stages, each of said N stages of said shift register means generating data pulse output of said sequential train of data pulses and being connected to a corresponding stage of said FFGM, each said stage of said FFGM generating a pulse of said N pulses in each of said first plurality and second plurality of timing pulse outputs.
Claim 4
Dependent Claim
114 words
A clock distribution circuit as recited in claim 2 wherein each said stage of said FFGM includes a feed forwArd connection to the next adjacent stage of said FFGM and a feed forward connection to each next corresponding adjacent stage of said shift register means, said feed forward connections containing information of the logic state of said timing output pulse of said particular FFGM stage in which said feed forward connections originate and being effective to inhibit the adjacent stages of said FFGM and said corresponding adjacent stages of said shift register means from generating output pulses when a fault mode is detected in said FFGM stage in which said feed forward connections originate.
Claim 5
Dependent Claim
81 words
A clock distribution circuit as recited in claim 3 wherein each stage of said FFGM includes a feedback connection to the corresponding stage of said shift register means containing information of the logic state of said timing output pulses of said particular FFGM stage in which said feedback connection originates, said feedback connection being effective to inhibit said corresponding stage of said shift register means when a fault mode is detected in said FFGM stage in which said feedback connection originates.
Claim 6
Dependent Claim
59 words
A clock distribution circuit as recited in claim 4 wherein each of said N stages of said shift register means includes an upper portion and each of said N stages of said shift register means except the Nth stage includes a lower portion, each of said upper portions and each of said lower portions including a flip-flop logic circuit.
Claim 7
Dependent Claim
50 words
A clock distribution circuit as recited in claim 5 wherein a first of said two mutually exclusive outputs of said phase feedback circuity means drives said shift register means to shift the logic output state of said lower portion flip-flop circuits into the next corresponding adjacent upper portion flip-flop circuits.
Claim 8
Dependent Claim
43 words
A clock distribution circuit as recited in claim 6 wherein said second mutual exclusive output of said phase feedback circuity means drives said shift register means to shift the logic output state of said upper flip-flop portion into said corresponding lower portion flip-flop.
References Cited (Backward Citations)
US3740660A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-12 | 1978-02-11 | 1978-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-12 | 1982-02-11 | 1982-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-12 | 1986-02-11 | 1986-08-13 | $7700.00 | Window Closed / Lapsed |