US5389831A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock generator for providing a pair of nonoverlapping clock signals with adjustable skew
Assignee: NXP BV
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Filing: 1992-12-17
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Granted: 1995-02-14
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Expires: 2012-12-17
Abstract
Abstract A clock generator for producing a pair of nonoverlapping clock signals. Each of a pair of output clock signals is generated by an associated AND gate having a first input connected directly to a clock input and having a second input connected through a delay element. Mechanisms are included to sense the amount of delay introduced by this delay element and to select a new delay value when the sensed delay is outside of an operating range.
Inventors
- 👤 Robert E. Eisenstadt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:28
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K5/1515
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
116 words
A clock generator comprising: a first AND gate having a first input connected to a clock input port, having a second input, and having an output port at which is produced a first output signal φ 1 ; a first delay element, for introducing a first delay time (D 3 ), electrically connected between the clock input port and the second input of the first AND gate; means coupled to said first delay element and responsive to said clock input, for sensing when s value of first delay time (D 3 ) is outside of an operating range and for adjusting the value of first delay time (D 3 ) to remain within this operating range.
Claim 2
Dependent Claim
116 words
A clock generator comprising: a first AND gate having a first input connected to a clock input port, having a second input, and having an output port at which is produced a first output signal φ 1 ; a first delay element, for introducing a first delay time (D 3 ), electrically connected between the clock input port and the second input of the first AND gate; means coupled to said first delay element and responsive to said clock input, for sensing when s value of first delay time (D 3 ) is outside of an operating range and for adjusting the value of first delay time (D 3 ) to remain within this operating range.
Claim 3
Dependent Claim
21 words
A dock generator as in claim 1 wherein said first delay element comprises a plurality of delay elements connected in series.
Claim 4
Dependent Claim
96 words
A clock generator as in claim 2 wherein said means for sensing and for adjusting said value of first delay time (D 3 ) comprises: means, connected to said clock input port and to said first delay element, for measuring said first delay time (D 3 ); and a first switching means, connected to said means for measuring first delay time (D 3 ) and connected to said first delay element, for directing a signal at an input of the first delay element through a selectable subset of its plurality of delay elements connected in series.
Claim 5
Dependent Claim
55 words
A clock generator as in claim 3 wherein said first switching means comprises: a first plurality of switches, each connected between the first input of the first AND gate and a node located between successive series delay elements within the first delay element, wherein only one of said switches is closed at any given time.
Claim 6
Dependent Claim
85 words
A clock generator as in claim 1 further comprising: an inverter having an input connected to the clock input port and having an output; a second AND gate having a first input connected to tho inverter output, having a second input, and having an output port at which is produced a second output signal φ 2 ; and a second delay element for introducing a second delay time (D 4 ) connected between the inverter output and the second input of the second AND gate.
Claim 7
Dependent Claim
55 words
A clock generator as in claim 5 further comprising: means, coupled to said second delay element and responsive to said clock input, for sensing when said second delay time D 4 is outside of an operating range and for adjusting the value of said second delay time D 4 to remain within this operating range.
Claim 8
Dependent Claim
21 words
A clock generator as in claim 6 wherein: said second delay element comprises a plurality of delay elements connected in series.
Claim 9
Dependent Claim
69 words
A clock generator as in claim 7 wherein said means for adjusting said second delay time (D 4 ) comprises: a second switching means, connected to said means for measuring said first delay time (D 3 ) and connected to said second delay element, for directing a signal at an input of the second delay element through a selectable subset of its plurality of delay elements connected in series.
Claim 10
Dependent Claim
54 words
A clock generator as in claim 8 wherein said switching means further comprises: a plurality of switches, each connected between the first input of the second AND gate and a node located between successive series delay elements within the second delay element, wherein only one of said switches is closed at any given time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-13 | 1998-08-15 | 1999-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-13 | 2002-08-15 | 2003-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-13 | 2006-08-15 | 2007-02-14 | $7700.00 | Window Closed / Lapsed |