Abstract Disclosed is a three-dimensional integrated memory cell having a high interior volume and a method for constructing the same. The cell makes use of a highly conductive substrate material for the bottom electrode, allowing construction of a thin substrate without intolerable resistance. The substrate of the preferred embodiment, for example, comprises titanium silicide. The preferred method comprises conformal deposition of a thin polysilicon layer within a high aspect ratio container, followed deposition of a suitable metal for silicidation with the polysilicon layer. The metal need not be conformal for this preferred method and may be deposited by sputter deposition. After silicidation, excess metal is selectively etched away to leave a conformal, thin yet highly conductive substrate material. The greater volume available due to this thinner substrate permits either scaling down of the cell dimension for more dense arrays with maintained capacitance per memory cell, or use of larger microstructures over the bottom electrode substrate, such as hemispherical grained silicon layers, for increased electrode surface area and greater capacitance.
A three-dimensional stacked capacitor for an integrated circuit, comprising: a bottom electrode substrate, the substrate comprising a metal silicide layer conforming to a three-dimensional shape; a bottom electrode textured layer over and directly contacting the silicide layer; a capacitor dielectric over and directly contacting the textured layer; and a top electrode over and directly contacting the capacitor dielectric, wherein the three-dimensional shape comprises a container having an outside width of less than about 9,000 Å.
Claim 2
Dependent Claim
75 words
A three-dimensional stacked capacitor for an integrated circuit, comprising: a bottom electrode substrate, the substrate comprising a metal silicide layer conforming to a three-dimensional shape; a bottom electrode textured layer over and directly contacting the silicide layer; a capacitor dielectric over and directly contacting the textured layer; and a top electrode over and directly contacting the capacitor dielectric, wherein the three-dimensional shape comprises a container having an outside width of less than about 9,000 Å.
Claim 3
Dependent Claim
24 words
The stacked capacitor of claim 1, wherein the textured layer comprises a layer of HSG silicon having a thickness greater than about 600 Å.
Claim 4
Dependent Claim
52 words
A container bottom electrode for an integrated circuit capacitor, the electrode comprising: a conductive substrate conforming to a container configuration, the substrate having a substantially uniform thickness of less than about 300 Å and including a metal silicide layer; a layer of hemispherical grained silicon overlying and directly contacting the silicide layer.
Claim 5
Dependent Claim
52 words
A container bottom electrode for an integrated circuit capacitor, the electrode comprising: a conductive substrate conforming to a container configuration, the substrate having a substantially uniform thickness of less than about 300 Å and including a metal silicide layer; a layer of hemispherical grained silicon overlying and directly contacting the silicide layer.
Claim 6
Dependent Claim
24 words
The container bottom electrode of claim 3, wherein the substrate is characterized by a resistivity of equal to or less than about 100 μΩ-cm.
Claim 7
Dependent Claim
15 words
The container bottom electrode of claim 3, wherein the silicide layer comprises a titanium silicide.