Formation of self-aligned capacitor contact module in stacked cyclindrical dram cell

Claim 1

A method of fabricating a capacitor on a semiconductor substrate having a device region formed therein comprising the steps of: a) depositing an insulating layer over a substrate surface, said substrate having said device region; b) forming a passivation layer over said insulating layer, said passivation layer having a top surface; c) forming a plug opening through said passivation layer and said insulating layer exposing said device region, said plug opening defined by sidewalls of said passivation layer and of said insulation layer; d) depositing a first polysilicon layer over said passivation layer and in said plug opening and making an electrical contact to said device region; e) anisotropically etching said first polysilicon layer so that a top surface of said first polysilicon layer is below said top surface of said passivation layer to form a plug; f) forming plug opening sidewall spacers on the sidewalls of said passivation layer and said insulation layer, said plug opening sidewall spacers having sidewalls; g) forming a first dielectric layer over said passivation layer, said plug opening sidewall spacers and said plug; h) forming a bottom electrode opening in said first dielectric layer, said bottom electrode opening at least partially exposing said plug, said bottom electrode opening defined by sidewalls of said first dielectric layer; i) forming a third polysilicon layer over said first dielectric layer, said plug opening sidewall spacers and said plug; j) forming a second dielectric layer over said third polysilicon layer and filling said bottom electrode opening; k) planarizing said second dielectric layer and said third polysilicon layer down to a top surface of said first dielectric layer and removing said third polysilicon layer on the top surface of said first dielectric layer, said third polysilicon layer forming a capacitor bottom electrode over said plug; l) removing said first dielectric layer and said second dielectric layer using a wet etch; and m) forming sequentially a capacitor dielectric layer and a fourth polysilicon layer over said capacitor bottom electrode thereby forming the capacitor.

Claim 2

A method of fabricating a capacitor on a semiconductor substrate having a device region formed therein comprising the steps of: a) depositing an insulating layer over a substrate surface, said substrate having said device region; b) forming a passivation layer over said insulating layer, said passivation layer having a top surface; c) forming a plug opening through said passivation layer and said insulating layer exposing said device region, said plug opening defined by sidewalls of said passivation layer and of said insulation layer; d) depositing a first polysilicon layer over said passivation layer and in said plug opening and making an electrical contact to said device region; e) anisotropically etching said first polysilicon layer so that a top surface of said first polysilicon layer is below said top surface of said passivation layer to form a plug; f) forming plug opening sidewall spacers on the sidewalls of said passivation layer and said insulation layer, said plug opening sidewall spacers having sidewalls; g) forming a first dielectric layer over said passivation layer, said plug opening sidewall spacers and said plug; h) forming a bottom electrode opening in said first dielectric layer, said bottom electrode opening at least partially exposing said plug, said bottom electrode opening defined by sidewalls of said first dielectric layer; i) forming a third polysilicon layer over said first dielectric layer, said plug opening sidewall spacers and said plug; j) forming a second dielectric layer over said third polysilicon layer and filling said bottom electrode opening; k) planarizing said second dielectric layer and said third polysilicon layer down to a top surface of said first dielectric layer and removing said third polysilicon layer on the top surface of said first dielectric layer, said third polysilicon layer forming a capacitor bottom electrode over said plug; l) removing said first dielectric layer and said second dielectric layer using a wet etch; and m) forming sequentially a capacitor dielectric layer and a fourth polysilicon layer over said capacitor bottom electrode thereby forming the capacitor.

Claim 3

The method of claim I wherein the formation of said plug opening sidewall spacers comprises: forming a second polysilicon layer over said passivation layer and said plug; and anisotropically etching said second polysilicon layer forming the plug opening sidewall spacers on the sidewalls of said passivation layer and said insulation layer.

Claim 6

The method of claim I wherein said substrate further includes transistors having source regions, drain regions, and gate electrodes, one of said source regions electrically connected to said plug in said active area.

Claim 8

The method of claim I wherein said plug opening has a diameter in a range of between about 0.3 and 0.5 μm and said bottom electrode opening having an open dimension in a range of between about 0.3 and 1.0 μm.

Claim 17

A method of fabricating a capacitor on a semiconductor substrate having a device region formed therein comprising the steps of: a) depositing an insulating layer composed of silicon oxide over a substrate surface; said substrate having said device region; b) forming a passivation layer composed of silicon nitride over said insulating layer, said passivation layer having a top surface; c) forming a plug opening through said passivation layer and said insulating layer exposing said device region; d) depositing a first polysilicon layer over said passivation layer and in said plug opening and making an electrical contact to said device region, said first polysilicon layer having an indentation over said plug opening; e) anisotropically etching said first polysilicon layer so that a top surface of said first polysilicon layer is below said top surface of said passivation layer to form a plug; f) forming plug opening sidewall spacers on sidewalls of said passivation layer and said insulation layer, said plug opening sidewall spacers having sidewalls; g) forming a first dielectric layer over said passivation layer, said plug opening sidewall spacers and said plug; h) forming a bottom electrode opening in said first dielectric layer, said bottom electrode opening at least partially exposing said plug, said bottom electrode opening defined by sidewalls of said first dielectric layer; i) forming a capacitor bottom electrode over said plug; j) removing said first dielectric layer using a wet etch; and k) forming sequentially a capacitor dielectric layer and a third polysilicon layer over said capacitor bottom electrode thereby forming the capacitor.

Claim 18

A method of fabricating a capacitor on a semiconductor substrate having a device region formed therein comprising the steps of: a) depositing an insulating layer composed of silicon oxide over a substrate surface; said substrate having said device region; b) forming a passivation layer composed of silicon nitride over said insulating layer, said passivation layer having a top surface; c) forming a plug opening through said passivation layer and said insulating layer exposing said device region; d) depositing a first polysilicon layer over said passivation layer and in said plug opening and making an electrical contact to said device region, said first polysilicon layer having an indentation over said plug opening; e) anisotropically etching said first polysilicon layer so that a top surface of said first polysilicon layer is below said top surface of said passivation layer to form a plug; f) forming plug opening sidewall spacers on sidewalls of said passivation layer and said insulation layer, said plug opening sidewall spacers having sidewalls; g) forming a first dielectric layer over said passivation layer, said plug opening sidewall spacers and said plug; h) forming a bottom electrode opening in said first dielectric layer, said bottom electrode opening at least partially exposing said plug, said bottom electrode opening defined by sidewalls of said first dielectric layer; i) forming a capacitor bottom electrode over said plug; j) removing said first dielectric layer using a wet etch; and k) forming sequentially a capacitor dielectric layer and a third polysilicon layer over said capacitor bottom electrode thereby forming the capacitor.