US5459094A
Expired / Lapsed
US
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Method for fabricating a capacitor cell in the semiconductor memory device having a step portion
Assignee: SK Hynix Inc
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Filing: 1994-02-08
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Granted: 1995-10-17
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Expires: 2014-02-08
Abstract
Abstract A semiconductor memory device including a plurality of memory cells arranged in a matrix manner, each of the memory cells including a transfer transistor constituted by a gate electrode, a gate insulating film, a source region and a drain region, and a charge storage capacitor constituted by a storage node, a dielectric film and a plate electrode, the storage node of the charge storage capacitor including a cylindrical lower electrode formed above the transfer transistor via an insulating layer formed on the transfer transistor and connected to one of the source region and the drain region of the transfer transistor, and a cover type upper electrode formed on the lower electrode and connected with the lower electrode. By the composite structure of the capacitor storage node including the lower structure having the cylinder shape and the cover type upper structure connected with the lower structure, it is possible to utilize efficiently a three-dimensional space structure and thereby achieve an increase in capacitance.
Inventors
- 👤 Young K. Jun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:42
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/043; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D1/042; H10D1/60; H10D1/68; H10D1/692; H10D1/696
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
273 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming a transfer transistor on a semiconductor substrate, said transfer transistor being constituted by a gate insulating film, a gate electrode, a source region and a drain region; forming a first insulating layer over the entire exposed surface of the resulting structure including the transfer transistor; selectively etching said first insulating layer such that one of said source region and said drain region of the transfer transistor is exposed; forming a first conduction layer over the entire exposed surface of the resulting structure; forming an insulating layer over said first conduction layer; selectively etching an outer portion of said insulating layer formed over the first conduction layer; etching the first conduction layer under a condition that the insulating layer formed over the first conduction layer is used as a mask; forming a second conduction layer over the entire exposed surface of the resulting structure; coating a photoresist film over said second conduction layer and patterning said photoresist film by use of a photolithography process to form a photoresist pattern having a dimension smaller than that of the remaining portion of the insulating layer formed over the first conduction layer; anisotropically dry-etching the second conduction layer under a condition that said photoresist pattern is used as a mask such that the insulating layer formed over the first conduction layer is partially exposed while side wall spacers are formed from the second conduction layer on side surfaces of the insulating layer formed over the first conduction layer, respectively; removing the photoresist pattern; and removing the insulating film formed over the first conduction layer.
Claim 2
Independent Claim
273 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming a transfer transistor on a semiconductor substrate, said transfer transistor being constituted by a gate insulating film, a gate electrode, a source region and a drain region; forming a first insulating layer over the entire exposed surface of the resulting structure including the transfer transistor; selectively etching said first insulating layer such that one of said source region and said drain region of the transfer transistor is exposed; forming a first conduction layer over the entire exposed surface of the resulting structure; forming an insulating layer over said first conduction layer; selectively etching an outer portion of said insulating layer formed over the first conduction layer; etching the first conduction layer under a condition that the insulating layer formed over the first conduction layer is used as a mask; forming a second conduction layer over the entire exposed surface of the resulting structure; coating a photoresist film over said second conduction layer and patterning said photoresist film by use of a photolithography process to form a photoresist pattern having a dimension smaller than that of the remaining portion of the insulating layer formed over the first conduction layer; anisotropically dry-etching the second conduction layer under a condition that said photoresist pattern is used as a mask such that the insulating layer formed over the first conduction layer is partially exposed while side wall spacers are formed from the second conduction layer on side surfaces of the insulating layer formed over the first conduction layer, respectively; removing the photoresist pattern; and removing the insulating film formed over the first conduction layer.
Claim 3
Dependent Claim
28 words
A method in accordance with claim 1, wherein said second conduction layer is partially connected with said first conduction layer via a part of said side wall spacers.
Claim 4
Dependent Claim
30 words
A method in accordance with claim 1, wherein said step of removing said insulating layer formed over said first conduction layer is carried out by use of wet etching process.
Claim 5
Dependent Claim
55 words
A method in accordance with claim 1, further comprising the steps of: forming a capacitor dielectric film over the entire exposed surface of the resulting structure after the removal of said remaining insulating film and said side wall spacers; and depositing a conduction material over said capacitor dielectric film, thereby forming a capacitor plate electrode.
Claim 6
Independent Claim
207 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming a transfer transistor on a semiconductor substrate, the transfer transistor including a gate insulating film, a gate electrode, a source region and a drain region; forming a first insulating layer over the semiconductor substrate and the transfer transistor; selectively etching the first insulating layer to form a contact hole through which one of the source region and the drain region is exposed; forming a first conduction layer over the contact hole and the first insulating layer; etching a central portion of the first conduction layer so that steps are formed thereon; forming a second insulating layer on the first conduction layer and the steps; selectively etching the second insulating layer such that the central portion of the first conduction layer is exposed; forming a second conduction layer over the second insulating layer and the central portion of the first conduction layer such that the second conduction layer is connected with the central portion of the first conduction layer; patterning the second conduction layer to form a lower storage node pattern; removing the second insulating layer formed on the first conduction layer; and patterning the first conduction layer to form a lower storage node pattern.
Claim 7
Independent Claim
207 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming a transfer transistor on a semiconductor substrate, the transfer transistor including a gate insulating film, a gate electrode, a source region and a drain region; forming a first insulating layer over the semiconductor substrate and the transfer transistor; selectively etching the first insulating layer to form a contact hole through which one of the source region and the drain region is exposed; forming a first conduction layer over the contact hole and the first insulating layer; etching a central portion of the first conduction layer so that steps are formed thereon; forming a second insulating layer on the first conduction layer and the steps; selectively etching the second insulating layer such that the central portion of the first conduction layer is exposed; forming a second conduction layer over the second insulating layer and the central portion of the first conduction layer such that the second conduction layer is connected with the central portion of the first conduction layer; patterning the second conduction layer to form a lower storage node pattern; removing the second insulating layer formed on the first conduction layer; and patterning the first conduction layer to form a lower storage node pattern.
Claim 8
Dependent Claim
26 words
A method in accordance with claim 5, wherein said step of etching the central portion of the first conduction layer uses an anisotropic dry etching process.
Claim 9
Dependent Claim
25 words
A method in accordance with claim 5, wherein said step of etching the central portion of the first conduction layer uses an isotropic etching process.
Claim 10
Dependent Claim
33 words
A method in accordance with claim 5, wherein said step of etching the central portion of the first conduction layer uses a combination of an anisotropic etching process and an isotropic etching process.
Claim 11
Dependent Claim
77 words
A method in accordance with claim 5, wherein said step of etching the central portion of the first conduction layer includes the steps of: forming a photoresist film over the first conduction layer; patterning the photoresist film using a photolithography process to form a photoresist film pattern and such that the central portion of the first conduction layer is exposed; and using the photoresist pattern as a mask, etching the central portion of the first conduction layer.
Claim 12
Dependent Claim
160 words
A method in accordance with claim 5, wherein said step of forming the first conduction layer includes the steps of: forming a photoresist film over the first conduction layer; patterning the photoresist film using a photolithography process to form a photoresist film pattern and such that an outer portion of the first conduction layer is exposed; using the photoresist pattern as a mask, etching the outer portion of the first conduction layer; removing the photoresist pattern; forming the second insulating layer over the first conduction layer; etching the second insulating layer such that first sidewall spacers are formed on sidewalls of the first conduction layer; using the sidewall spacers as a mask, etching the first conduction layer to thereby form the steps on the first conduction layer; forming a third insulating layer over the first conduction layer and the first sidewall spacers; and etching the third insulating layer such that second sidewall spacers are formed on the first conduction layer.
Claim 13
Dependent Claim
21 words
A method in accordance with claim 5, wherein said step of removing the second insulating layer uses a wet etching process.
Claim 14
Dependent Claim
49 words
A method in accordance with claim 5, further comprising the steps of: forming a capacitor dielectric film over the upper and lower storage nodes after said patterning of the first conduction layer step; and depositing a conduction material over the capacitor dielectric film, thereby forming a capacitor plate electrode.
Claim 15
Independent Claim
278 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming a transfer transistor on a semiconductor substrate, the transfer transistor including a gate insulating film, a gate electrode, a source region and a drain region; forming a first insulating layer over the semiconductor substrate and the transfer transistor; selectively etching the first insulating layer to form a contact hole through which one of the source region and the drain region of the transfer transistor is exposed; forming a first conduction layer over the contact hole and the first insulating layer; selectively etching an outer portion of the first conduction layer such that steps are formed on the first conduction layer; forming a second insulating layer over the first conduction layer; selectively etching the second insulating layer such that a central portion of the first conduction layer is exposed; using the second insulating layer as a mask, etching the first conduction layer; forming a second conduction layer over the first conduction layer and the second insulating layer; coating photoresist film over the second conduction layer and patterning the photoresist film using a photolithography process to form a photoresist pattern and such that an outer portion of the second conduction layer is exposed; using the photoresist pattern as a mask, anisotopically dry etching the second conduction layer and the second insulating layer formed over the first conduction layer to thereby form sidewall spacers on the steps of the first conduction layer; using the photoresist pattern and the sidewall spacers as a mask, etching the first conduction layer; removing the photoresist pattern; and removing the second insulating film formed over the first conduction layer and the sidewall spacers.
Claim 16
Independent Claim
278 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming a transfer transistor on a semiconductor substrate, the transfer transistor including a gate insulating film, a gate electrode, a source region and a drain region; forming a first insulating layer over the semiconductor substrate and the transfer transistor; selectively etching the first insulating layer to form a contact hole through which one of the source region and the drain region of the transfer transistor is exposed; forming a first conduction layer over the contact hole and the first insulating layer; selectively etching an outer portion of the first conduction layer such that steps are formed on the first conduction layer; forming a second insulating layer over the first conduction layer; selectively etching the second insulating layer such that a central portion of the first conduction layer is exposed; using the second insulating layer as a mask, etching the first conduction layer; forming a second conduction layer over the first conduction layer and the second insulating layer; coating photoresist film over the second conduction layer and patterning the photoresist film using a photolithography process to form a photoresist pattern and such that an outer portion of the second conduction layer is exposed; using the photoresist pattern as a mask, anisotopically dry etching the second conduction layer and the second insulating layer formed over the first conduction layer to thereby form sidewall spacers on the steps of the first conduction layer; using the photoresist pattern and the sidewall spacers as a mask, etching the first conduction layer; removing the photoresist pattern; and removing the second insulating film formed over the first conduction layer and the sidewall spacers.
Claim 17
Dependent Claim
16 words
A method in accordance with claim 13, wherein the second insulating layer comprises a nitride film.
Claim 18
Dependent Claim
52 words
A method in accordance with claim 13, further comprising the steps of: forming a capacitor dielectric film over the first and second conduction layers after said removing the second insulating film and the sidewall spacers step; and depositing a conduction material over the capacitor dielectric film thereby forming a capacitor plate electrode.
Claim 19
Independent Claim
252 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming a transfer transistor on a semiconductor substrate, the transfer transistor including a gate insulating film, a gate electrode, a source region and a drain region; forming a first insulating layer over the semiconductor substrate and the transfer transistor; selectively etching the first insulating layer to form a contact hole through which one of the source region and the drain region of the transfer transistor is exposed; forming a first conduction layer over the contact hole and the first insulating layer; forming a second insulating layer over the first conduction layer; selectively etching an outer portion of the second insulating layer; using the second insulating layer as a mask, etching the first conduction layer; forming a second conduction layer over the first conduction layer and the second insulating layer; coating a photoresist film over the second conduction layer and patterning the photoresist film using a photolithography process to form a photoresist pattern having a dimension smaller than that of the remaining portion of the second insulating layer formed over the first conduction layer; using the photoresist pattern as a mask, anisotopically dry etching the second conduction layer such that the second insulating layer formed over the first conduction layer is partially exposed while sidewall spacers are formed from the second insulating layer on sidewalls of the second insulating layer and the first conduction layer; removing the photoresist pattern; and removing the second insulating film formed over the first conduction layer.
Claim 20
Independent Claim
252 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming a transfer transistor on a semiconductor substrate, the transfer transistor including a gate insulating film, a gate electrode, a source region and a drain region; forming a first insulating layer over the semiconductor substrate and the transfer transistor; selectively etching the first insulating layer to form a contact hole through which one of the source region and the drain region of the transfer transistor is exposed; forming a first conduction layer over the contact hole and the first insulating layer; forming a second insulating layer over the first conduction layer; selectively etching an outer portion of the second insulating layer; using the second insulating layer as a mask, etching the first conduction layer; forming a second conduction layer over the first conduction layer and the second insulating layer; coating a photoresist film over the second conduction layer and patterning the photoresist film using a photolithography process to form a photoresist pattern having a dimension smaller than that of the remaining portion of the second insulating layer formed over the first conduction layer; using the photoresist pattern as a mask, anisotopically dry etching the second conduction layer such that the second insulating layer formed over the first conduction layer is partially exposed while sidewall spacers are formed from the second insulating layer on sidewalls of the second insulating layer and the first conduction layer; removing the photoresist pattern; and removing the second insulating film formed over the first conduction layer.
Claim 21
Dependent Claim
27 words
A method in accordance with claim 16, wherein the second conduction layer is partially connected with the first conduction layer via a part of the sidewall spacers.
Claim 22
Dependent Claim
21 words
A method in accordance with claim 16, wherein said step of removing the second insulating layer uses a wet etching process.
Claim 23
Dependent Claim
47 words
A method in accordance with claim 16, further comprising the steps of: after said second insulating film removing step, forming a capacitor dielectric film over the first and second conduction layers; and depositing a conduction material over the capacitor dielectric film, thereby forming a capacitor plate electrode.
Claim 24
Dependent Claim
62 words
A method in accordance with claim 5, further comprising the steps of: forming a third insulating layer over the second insulating layer and the first conduction layer, after selectively etching the second insulating layer; and etching the third insulating layer so that sidewall spacers are formed on sidewalls of the second insulating layer and the central portion of the first conduction layer.
Claim 25
Dependent Claim
43 words
A method in accordance with claim 5, wherein said step of selectively etching the second insulating film includes the step of selectively etching the second insulating layer using a photolithography process, such that the central portion of the first conduction layer is exposed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-16 | 1999-04-17 | 1999-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-16 | 2003-04-17 | 2003-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-16 | 2007-04-17 | 2007-10-17 | $7700.00 | Window Closed / Lapsed |