EP0398569A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Dynamic random access memory device
Assignee: Fujitsu Ltd
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Filing: 1990-05-08
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Granted: —
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Expires: 2010-05-08
Abstract
Abstract A DRAM including a peripheral circuit (3) and a memory cell (2) has a fin structure capacitor (6) overlying and separated from a transfer gate transistor (6) by a silicon nitride layer (18). A conductive layer (13A) which forms an electrode (13) of the capacitor (6) the silicon nitride layer (18A) is removed from above the peripheral circuit (3) before contact windows (31,32) are opened up through insulating layers (16,17) to the surface of a semiconductor element (22) formed in the peripheral circuit (3). This improves the aspect ratio of the contact windows and prevents breakage of subsequently applied wiring.
Inventors
- 👤 Shinichirou 203 Copo Hichifukudaiichi Ikemasu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 11:52
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
107 words
A method of making a DRAM including a peripheral circuit (3) and a memory cell (2) having a fin structure capacitor (6) overlying and separated from a transfer gate transistor (6) by a silicon nitride layer (18), in which a conductive layer (13A) forming an electrode (13) of the capacitor (6) is removed from above the peripheral circuit (3) before contact windows (31,32) are opened up through insulating layers, (16,17) to the surface of a semiconductor element (22) formed in the peripheral circuit (3); characterised in that the silicon nitride layer (18A) is removed from above the peripheral circuit (3) before opening up the contact windows (31,32).
Claim 2
Independent Claim
107 words
A method of making a DRAM including a peripheral circuit (3) and a memory cell (2) having a fin structure capacitor (6) overlying and separated from a transfer gate transistor (6) by a silicon nitride layer (18), in which a conductive layer (13A) forming an electrode (13) of the capacitor (6) is removed from above the peripheral circuit (3) before contact windows (31,32) are opened up through insulating layers, (16,17) to the surface of a semiconductor element (22) formed in the peripheral circuit (3); characterised in that the silicon nitride layer (18A) is removed from above the peripheral circuit (3) before opening up the contact windows (31,32).
Claim 3
Dependent Claim
29 words
A method according to claim 1, in which the silicon nitride layer (18A) and the conductive layer (13A) are removed by the same etchant in a single etching step.
Claim 4
Independent Claim
180 words
A method of producing a semiconductor memory device wherein said method comprises the steps of: forming insulation film layers (16,17,18) onto a first semiconductor element (4) and a second semiconductor element (4), said first semiconductor element (22), said first semiconductor element (4) being used to constitute a memory cell (MC) formed on a semiconductor substrate (1), and said second semiconductor element (22) being used to constitute a peripheral circuit (3) other than said memory cell (MC) formed on the same semiconductor substrate (1); forming a conductive layer (13) onto the top insulation layer (18) of said insulation film layers (16,17,18), and said conductive layer (13) being used in a memory cell portion (2) including said memory cell (MC); removing said conductive layer (13; 13A) ) and at least said top insulation layer (18) formed above said second semiconductor element (22); and making a contact hole (31,32) passing through said insulation film layers (16,17) at a location where the top insulation layer (18) and conductive layer (13A) have been removed, and reaching to a surface of said second semiconductor element (22).
Claim 5
Independent Claim
180 words
A method of producing a semiconductor memory device wherein said method comprises the steps of: forming insulation film layers (16,17,18) onto a first semiconductor element (4) and a second semiconductor element (4), said first semiconductor element (22), said first semiconductor element (4) being used to constitute a memory cell (MC) formed on a semiconductor substrate (1), and said second semiconductor element (22) being used to constitute a peripheral circuit (3) other than said memory cell (MC) formed on the same semiconductor substrate (1); forming a conductive layer (13) onto the top insulation layer (18) of said insulation film layers (16,17,18), and said conductive layer (13) being used in a memory cell portion (2) including said memory cell (MC); removing said conductive layer (13; 13A) ) and at least said top insulation layer (18) formed above said second semiconductor element (22); and making a contact hole (31,32) passing through said insulation film layers (16,17) at a location where the top insulation layer (18) and conductive layer (13A) have been removed, and reaching to a surface of said second semiconductor element (22).
Claim 6
Dependent Claim
90 words
A method according to claim 3, in which the step of forming insulation film layers comprises: a step of forming a first insulation film layer (16) onto the first semiconductor element (4) and the second semiconductor element (22); a step of forming an intermediate conductive layer (5) over the substrate (1), the intermediate conductive layer (5) being patterned in the shape of a bit line and electrically connected to the first semiconductor element (4); and a step of forming a second insulation film layer (18) extending over said substrate (1).
Claim 7
Dependent Claim
40 words
A method according to claim 3 or 4, wherein said memory cell (MC) is constituted by said first semiconductor element (4) and a capacitor element (6) formed onto said top insulation layer (18) and above said first semiconductor element (4).
Claim 8
Dependent Claim
34 words
A method according to claim 3, 4 or 5, wherein said top insulation layer (18) and said conductive layer (13) are used to form said capacitor element (6) above said first semiconductor element (4).
Claim 9
Independent Claim
51 words
A method according to any one of claims 3 to 6, wherein said conductive layer (13) is constituted by a polycrystal silicon layer, said top insulation layer (18) is constituted by a Si₃N₄ film layer, and said insulation layers (16,17) except the top layer (18) are constituted by SiO₂ film layers.
Claim 10
Dependent Claim
40 words
A method according to claim 7, wherein said conductive layer (13; 13A) of polycrystal silicon and said top insulation layer (18) of Si₃N₄ formed on said second semiconductor element (22) are removed by an etching method using a mixed gas.
Claim 11
Dependent Claim
19 words
A method according to claim 7, wherein said mixed gas is made of sulfur hexafluoride (SF₆) and a freon.
Claim 12
Independent Claim
39 words
A method according to any one of claims 3 to 9, wherein said method further comprises a step of forming another insulation film layer (17) between said first insulation film layer (16) and said top insulation film layer (18).
Claim 13
Dependent Claim
184 words
A semiconductor memory device having a memory cell portion (2) including a plurality of memory cells (MC) and a peripheral circuit (3), wherein said device comprises: a first semiconductor element (4), formed on a semiconductor substrate (1), for constituting said memory cell (MC); a second semiconductor element (22), formed on said semiconductor substrate (1), for constituting said peripheral circuit (3); a first insulation film layer (16), formed onto said first semiconductor element (4) and said second semiconductor element (22); a second insulation film layer (18), formed onto said first insulation film layer (16) only in the area of said memory cell portion (2); a conductive layer (13) formed onto said second insulation film layer (18) only in the area of said memory cell portion (2); and a contact hole (31, 32), provided in said second semiconductor element (22), for constructing said peripheral circuit (3) by wiring, and said contact hole (31, 32) being formed to pass through at least said first insulation film layer (16) and reach to a surface of said second semiconductor element (22), without passing through said second conductive layer (18).
Claim 14
Dependent Claim
184 words
A semiconductor memory device having a memory cell portion (2) including a plurality of memory cells (MC) and a peripheral circuit (3), wherein said device comprises: a first semiconductor element (4), formed on a semiconductor substrate (1), for constituting said memory cell (MC); a second semiconductor element (22), formed on said semiconductor substrate (1), for constituting said peripheral circuit (3); a first insulation film layer (16), formed onto said first semiconductor element (4) and said second semiconductor element (22); a second insulation film layer (18), formed onto said first insulation film layer (16) only in the area of said memory cell portion (2); a conductive layer (13) formed onto said second insulation film layer (18) only in the area of said memory cell portion (2); and a contact hole (31, 32), provided in said second semiconductor element (22), for constructing said peripheral circuit (3) by wiring, and said contact hole (31, 32) being formed to pass through at least said first insulation film layer (16) and reach to a surface of said second semiconductor element (22), without passing through said second conductive layer (18).
Claim 15
Dependent Claim
78 words
A semiconductor memory device as claimed in claim 11, wherein device further comprises a capacitor element (6), formed onto said second insulation film layer (18) and above said first semiconductor element (4), for constituting said memory cell (MC); said capacitor element (6) comprises a first polycrystal silicon layer (11) for forming a storage electrode (11A, 11B), a capacitor insulation film (12) covering said storage electrode (11A, 11B), and a second polycrystal silicon layer (13) of said conductive layer.
Claim 16
Dependent Claim
23 words
A semiconductor memory device as claimed in claim 12, wherein said capacitor element (6) comprises a plurality of storage electrodes (11a, 11b, 11c).
Claim 17
Dependent Claim
37 words
A semiconductor memory device as claimed in claim 11, 12 or 13 wherein said device further comprises a third insulation film layer (17) between said first insulation film layer (16) and said second insulation film layer (18).
Claim 18
Dependent Claim
43 words
A semiconductor memory device as claimed in claim 11, 12, 13 or 14, wherein said first and third insulation film layers (16, 17) are constituted by SiO₂ film layers, and said second insulation film layer (18) is constituted by a Si₃N₄ film layer.
References Cited (Backward Citations)
No citation records indexed.
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