US5274258A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density semiconductor memory device (MBC cell)
Assignee: Samsung Electronics Co Ltd
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Filing: 1991-06-14
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Granted: 1993-12-28
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Expires: 2011-06-14
Abstract
Abstract A high-density semiconductor memory device and its manufacturing method are disclosed. The device has a plurality of memory cells, each consisting of one transistor and one capacitor on a substrate in a matrix form. The capacitor, in contact with the source region of the transistor, consists of a storage electrode having a hollow cylindrical electrode with a wall of predetermined thickness, and a column electrode surrounded by the cylindrical electrode. The capacitor further comprises a plurality of bars, a base plate electrode connecting the cylindrical and column electrodes to each other, a dielectric layer coating the whole surface of the storage electrode, and a plate electrode formed on top of the dielectric layer. According to this invention, a greater capacitance may be obtained while avoiding current leakage and the disparity of cell capacitance problems involved with a conventional stack-type capacitor having a ringed structure.
Inventors
- 👤 Ji-hong Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:52
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/043; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; H10D1/716
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
108 words
A high-density semiconductor memory device having a plurality of memory cells each comprising one transistor having a source region and a drain region, and one capacitor in matrix form on a semiconductor substrate, in which said capacitor further comprises: a storage electrode disposed adjacent to the source region of said transistor having a column electrode comprising a plurality of bars, an outer peripheral electrode completely enclosing said column electrode, and a base plate electrode having a lower surface, connected to said column electrode and said outer peripheral electrode; a dielectric layer coating an entire surface of said storage electrode; and a plate electrode formed on said dielectric layer.
Claim 2
Dependent Claim
108 words
A high-density semiconductor memory device having a plurality of memory cells each comprising one transistor having a source region and a drain region, and one capacitor in matrix form on a semiconductor substrate, in which said capacitor further comprises: a storage electrode disposed adjacent to the source region of said transistor having a column electrode comprising a plurality of bars, an outer peripheral electrode completely enclosing said column electrode, and a base plate electrode having a lower surface, connected to said column electrode and said outer peripheral electrode; a dielectric layer coating an entire surface of said storage electrode; and a plate electrode formed on said dielectric layer.
Claim 3
Dependent Claim
19 words
A high density semiconductor memory device according to claim 1, wherein said outer peripheral electrode comprises a hollow cylinder.
Claim 4
Dependent Claim
19 words
A high-density semiconductor memory device according to claim 1, wherein said storage electrode comprises at least one conductive layer.
Claim 5
Dependent Claim
20 words
A high-density semiconductor memory device according to claim 1, wherein the lower surface of said base plate electrode is flat.
Claim 6
Dependent Claim
23 words
A high-density semiconductor memory device according to claim 1, wherein said base plate electrode is formed along the contours of said transistor structure.
Claim 7
Dependent Claim
26 words
A high-density semiconductor memory device according to claim 1, wherein said capacitor utilizes said lower surface of said base plate electrode as an effective capacitance region.
Claim 8
Dependent Claim
19 words
A high-density semiconductor memory device according to claim 1, further comprising bit lines which are disposed below said capacitor.
Claim 9
Dependent Claim
16 words
A high-density semiconductor memory device as claimed in claim 7, wherein said bit lines are planerized.
Claim 10
Dependent Claim
25 words
A high-density semiconductor memory device according to claim 7, wherein said bit lines of said memory device are formed after the formation of said capacitor.
Claim 11
Dependent Claim
113 words
A high-density semiconductor memory device having a plurality of memory cells each comprising one transistor having a source region and a drain region, and one capacitor in matrix form on a semiconductor substrate, in which said capacitor further comprises: a storage electrode disposed adjacent to the source region of said transistor having a column electrode comprising a plurality of bars of different shapes and sizes, an outer peripheral electrode completely enclosing said column electrode, and a base plate electrode having a lower surface, connected to said column electrode and said outer peripheral electrode; a dielectric layer coating an entire surface of said storage electrode; and a plate electrode formed on said dielectric layer.
Claim 12
Dependent Claim
113 words
A high-density semiconductor memory device having a plurality of memory cells each comprising one transistor having a source region and a drain region, and one capacitor in matrix form on a semiconductor substrate, in which said capacitor further comprises: a storage electrode disposed adjacent to the source region of said transistor having a column electrode comprising a plurality of bars of different shapes and sizes, an outer peripheral electrode completely enclosing said column electrode, and a base plate electrode having a lower surface, connected to said column electrode and said outer peripheral electrode; a dielectric layer coating an entire surface of said storage electrode; and a plate electrode formed on said dielectric layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-27 | 1997-06-28 | 1997-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-27 | 2001-06-28 | 2001-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-27 | 2005-06-28 | 2005-12-28 | $7700.00 | Window Closed / Lapsed |