US5332685A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a DRAM cell
Assignee: SK Hynix Inc
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Filing: 1993-06-24
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Granted: 1994-07-26
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Expires: 2013-06-24
Abstract
Abstract Disclosed is a novel DRAM manufacturing method to reduce difficulties due to the high aspect ratio of contact hole for storage electrode. The method comprises the steps of formation of a contact plug on contact areas of bit line and storage electrode at the same time and then, formation of a bit line that is in contact with the contact plug for bit line and finally, making a storage electrode that is as high as the bit line contact with the contact plug for storage electrode.
Inventors
- 👤 Young J. Park
- 👤 Seok H. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:01
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/48; H10B12/485; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/31; H10B12/482; Y; Y10; Y10S; Y10S438/00; Y10S438/907
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
286 words
A method of manufacturing a DRAM cell comprising the steps of: forming a word line having an oxide layer spacer on its side wall, on a silicon substrate; forming a first insulating layer on the entire silicon substrate; forming several contact holes by etching out some portions of the first insulating layer using contact masks for bit line and storage electrode; forming a contact plug by filling the contact holes with a conductive material; depositing a conducting layer fox bit line and a second insulating layer on the substrate including said first insulating layer and contact plug, and forming a second insulating layer pattern and bit line pattern on the contact plug for bit line by the etching process using a bit line mask; forming an insulating layer spaces on the side walls of the bit line pattern and the second insulating layer pattern; forming a third insulating layer over the entire substrate, and etching back until the underlying second insulating layer is exposed; forming a photoresist layer pattern for storage electrode contact mask on the third insulating layer; isotropically etching the third insulating layer that has been exposed to the contact plug for storage electrode, and removing the photoresist layer pattern for storage electrode contact mask; depositing a conducting layer for storage electrode over the entire substrate, and coating a photoresist layer over it; forming a storage electrode pattern by etching back the photoresist layer and conducting layer for storage electrode until the third insulating layer and the second insulating layer are exposed; removing the remaining photoresist layer, and wet etching out third insulating layer to expose the storage electrode; and forming a capacitor dielectric layer and plate electrode on top of the storage electrode.
Claim 2
Independent Claim
286 words
A method of manufacturing a DRAM cell comprising the steps of: forming a word line having an oxide layer spacer on its side wall, on a silicon substrate; forming a first insulating layer on the entire silicon substrate; forming several contact holes by etching out some portions of the first insulating layer using contact masks for bit line and storage electrode; forming a contact plug by filling the contact holes with a conductive material; depositing a conducting layer fox bit line and a second insulating layer on the substrate including said first insulating layer and contact plug, and forming a second insulating layer pattern and bit line pattern on the contact plug for bit line by the etching process using a bit line mask; forming an insulating layer spaces on the side walls of the bit line pattern and the second insulating layer pattern; forming a third insulating layer over the entire substrate, and etching back until the underlying second insulating layer is exposed; forming a photoresist layer pattern for storage electrode contact mask on the third insulating layer; isotropically etching the third insulating layer that has been exposed to the contact plug for storage electrode, and removing the photoresist layer pattern for storage electrode contact mask; depositing a conducting layer for storage electrode over the entire substrate, and coating a photoresist layer over it; forming a storage electrode pattern by etching back the photoresist layer and conducting layer for storage electrode until the third insulating layer and the second insulating layer are exposed; removing the remaining photoresist layer, and wet etching out third insulating layer to expose the storage electrode; and forming a capacitor dielectric layer and plate electrode on top of the storage electrode.
Claim 3
Dependent Claim
32 words
The method according to claim 1 wherein said third insulating layer has an etching ratio that is different from that of the first and second insulating layers, and the insulating layer spacer.
Claim 4
Dependent Claim
14 words
The method according to claim 2 wherein said third insulating layer is BPSG layer.
Claim 5
Dependent Claim
21 words
The method according to claim 2 wherein said first and second insulating layers, and said insulating layer spacer are oxide layer.
Claim 6
Dependent Claim
39 words
The method according to claim 1 wherein said formation of a contact plug comprises the steps of formation of a conducting layer over the entire substrate and etching back to leave the conducting layer only on the contact holes.
Claim 7
Dependent Claim
30 words
The method according to claim 1 wherein said formation of a contact plug comprises the step of selectively depositing a polysilicon layer or metal layer only onto the contact holes.
Claim 8
Dependent Claim
22 words
The method according to claim 1 further comprising the step of forming a silicide layer on the conducting layer for bit line.
Claim 9
Dependent Claim
23 words
The method according to claim 1 wherein said photoresist layer and conducting layer for storage electrode are etched back with identical etching ratios.
References Cited (Backward Citations)
US5229314A
Cited
US5219780A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-25 | 1998-01-24 | 1998-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-25 | 2002-01-24 | 2002-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-25 | 2006-01-24 | 2006-07-26 | $7700.00 | Window Closed / Lapsed |