Patent US5757693A successfully refreshed from Google Patents.
US5757693A
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Gain memory cell with diode
Assignee: Cavium International
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Filing: 1997-02-19
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Granted: 1998-05-26
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Expires: 2017-02-19
Abstract
Abstract A gain cell in a memory array having read and write bitlines and wordlines, wherein the gain cell comprises a write transistor, a storage node, a read transistor, and a diode is disclosed. The write transistor allows the value of the write bitline to be stored onto the storage node when activated by the write wordline. The read transistor, which allows the stored value to be read, is coupled to the storage node and to the read bitline via the diode. The diode prevents the conduction of the read transistor in the opposite direction, thus preventing read interference from other cells and reducing bitline capacitance.
Inventors
- 👤 Russell J. Houghton
- 👤 Claude L. Bertin
- 👤 John A. Fifield
- 👤 Christopher P. Miller
- 👤 William R. Tonti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/403; G11C11/405
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
112 words
A gain cell circuit for a memory array having at least one read and write bitline and wordline, the gain cell circuit comprising: a write transistor, coupled to the write bitline and the write wordline; a storage node, coupled to said write transistor, for storing a value from the write bitline when said write transistor is activated by the write wordline; a read transistor, coupled to said storage node and the read wordline; and a diode, coupled between the read transistor and the read bitline, for allowing a read-out of said value when said gain cell is selected and preventing a read-out of said value when said gain cell is not selected.
Claim 2
Dependent Claim
112 words
A gain cell circuit for a memory array having at least one read and write bitline and wordline, the gain cell circuit comprising: a write transistor, coupled to the write bitline and the write wordline; a storage node, coupled to said write transistor, for storing a value from the write bitline when said write transistor is activated by the write wordline; a read transistor, coupled to said storage node and the read wordline; and a diode, coupled between the read transistor and the read bitline, for allowing a read-out of said value when said gain cell is selected and preventing a read-out of said value when said gain cell is not selected.
Claim 3
Dependent Claim
43 words
The circuit of claim 1, wherein said write transistor is a field-effect transistor having a gate, a source and a drain, said gate coupled to the write wordline, said source coupled to the write bitline, and said drain coupled to said storage node.
Claim 4
Dependent Claim
14 words
The circuit of claim 2, wherein said field-effect transistor is an n-channel field-effect transistor.
Claim 5
Dependent Claim
14 words
The circuit of claim 2, wherein said field-effect transistor is a p-channel field-effect transistor.
Claim 6
Dependent Claim
53 words
The circuit of claim 1, wherein said read transistor is a field-effect transistor having a gate, a source and a drain, said gate coupled to said storage node, said source coupled to the read wordline, and said drain coupled to said diode, said read transistor providing a nondestructive read-out of said storage node.
Claim 7
Dependent Claim
14 words
The circuit of claim 5, wherein said field-effect transistor is an n-channel field-effect transistor.
Claim 8
Dependent Claim
14 words
The circuit of claim 5, wherein said field-effect transistor is a p-channel field-effect transistor.
Claim 9
Dependent Claim
12 words
The circuit of claim 1, wherein said diode is a Schottky diode.
Claim 10
Independent Claim
84 words
A method of preventing read interference in a gain cell memory array having at least one gain cell with a read transistor and a read bitline comprising the steps of: a) providing a diode coupled between said read transistor and said read bitline in said gain cell; b) storing a value in the gain cell; c) reading out said value when said gain cell is selected; and d) preventing a read-out of said value with said diode when said gain cell is not selected.
Claim 11
Independent Claim
84 words
A method of preventing read interference in a gain cell memory array having at least one gain cell with a read transistor and a read bitline comprising the steps of: a) providing a diode coupled between said read transistor and said read bitline in said gain cell; b) storing a value in the gain cell; c) reading out said value when said gain cell is selected; and d) preventing a read-out of said value with said diode when said gain cell is not selected.
Claim 12
Dependent Claim
25 words
The method of claim 9, wherein step a) further comprises the step of: activating a write transistor to write said value in said gain cell.
Claim 13
Dependent Claim
18 words
The method of claim 10, further comprising the step of: providing a field-effect transistor for said write transistor.
Claim 14
Dependent Claim
37 words
The method of claim 9, wherein step c) further comprises the step of: activating a read transistor for reading said value in said gain cell, wherein said read transistor provides a nondestructive read-out of said gain cell.
Claim 15
Dependent Claim
18 words
The method of claim 12, further comprising the step of: providing a field-effect transistor for said read transistor.
Claim 16
Dependent Claim
109 words
A memory array system comprising: a read and write bitline; a read and write wordline; and a gain cell including: a write transistor, coupled to the write bitline and the write wordline; a storage node, coupled to said write transistor, for storing a value from the write bitline when said write transistor is activated by the write wordline; a read transistor, coupled to said storage node and the read wordline; and a diode, coupled between the read transistor and the read bitline, for allowing a read-out of said value when said gain cell is selected and preventing a readout of said value when said gain cell is not selected.
Claim 17
Dependent Claim
109 words
A memory array system comprising: a read and write bitline; a read and write wordline; and a gain cell including: a write transistor, coupled to the write bitline and the write wordline; a storage node, coupled to said write transistor, for storing a value from the write bitline when said write transistor is activated by the write wordline; a read transistor, coupled to said storage node and the read wordline; and a diode, coupled between the read transistor and the read bitline, for allowing a read-out of said value when said gain cell is selected and preventing a readout of said value when said gain cell is not selected.
Claim 18
Dependent Claim
43 words
The system of claim 14, wherein said write transistor is a field-effect transistor having a gate, a source and a drain, said gate coupled to the write wordline, said source coupled to the write bitline, and said drain coupled to said storage node.
Claim 19
Dependent Claim
14 words
The system of claim 15, wherein said field-effect transistor is an n-channel field-effect transistor.
Claim 20
Dependent Claim
14 words
The system of claim 15, wherein said field-effect transistor is a p-channel field-effect transistor.
Claim 21
Dependent Claim
54 words
The system of claim 14, wherein said read transistor is an n-channel field-effect transistor having a gate, a source and a drain, said gate coupled to said storage node, said source coupled to the read wordline, and said drain coupled to said diode, said read transistor providing a nondestructive read-out of said storage node.
Claim 22
Dependent Claim
43 words
The system of claim 14, wherein said read transistor is a p-channel field-effect transistor having a gate, a source and a drain, said gate coupled to said storage node, said source coupled to the read wordline, and said drain coupled to said diode.
Claim 23
Dependent Claim
12 words
The system of claim 14, wherein said diode is a Schottky diode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-25 | 2001-11-24 | 2002-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-25 | 2005-11-24 | 2006-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-25 | 2009-11-24 | 2010-05-26 | $7700.00 | Window Closed / Lapsed |