US4431305A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density DC stable memory cell
Assignee: International Business Machines Corp
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Filing: 1981-07-30
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Granted: 1984-02-14
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Expires: 2001-07-30
Abstract
Abstract An electronic data storage or memory array having DC stable memory cells which utilize the principle of a unique substrate biasing mechanism, whereby a channel region defined by resistive substrate material and formed under a controlled electrode becomes "pinched off" and, in the process, so affects the DC potential at that electrode as to maintain the pinched off condition. Consequently, the memory cell becomes established in a first DC stable state ("one" state). The principle is preferably embodied in a field effect transistor (FET), the resistive channel region being connected in a DC conductive path to a fixed resistor and a potential source. Accordingly, when appropriate signal levels representing a binary "one" are applied to word and bit lines connected to a first controlling, or gate, electrode and to a second controlling electrode, respectively, of the FET, the described pinch-off occurs, with concomitantly high resistance in the DC path, such that the potential adjacent the controlled electrode is maintained in the "one" state that was initiated by the signals on the word and bit lines. On the other hand, when signals representing a "zero" are applied to the same controlling electrodes, the resistive channel region under the controlled electrode is no longer pinched-off, whereby the memory cell becomes established in the second or "zero" DC stable state. Means for reading the stored data in the cell are integrated with the cell.
Inventors
- 👤 Shashi D. Malaviya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; H; H10; H10B; H10B10/00; H10B10/10
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
197 words
A DC-stable memory cell comprising: an integrated junction field effect transistor, having a controlled electrode and first and second controlling electrodes, said controlled electrode being the gate electrode of said junction field effect transistor; a resistor having a fixed value of resistance coupled to said controlled electrode of said transistor; at least one word line and at least one bit line connected to said memory cell; said controlled electrode being held at one of two DC stable potential levels, indicative of one of two binary states, as a function of voltage levels applied by means of the word line and the bit line; and a variable impedance means integrated in a channel adjacent to said controlled electrode, the impedance of said variable impedance means being altered by the controlled electrode, which is operable to pinch off said channel responsive to a set of voltage levels applied by means of the word line and the bit line, such that when said variable impedance is at a low impedance the memory cell is sustained in a first binary state, and when said variable impedance is at a high impedance the memory cell is sustained in a second binary state.
Claim 2
Dependent Claim
197 words
A DC-stable memory cell comprising: an integrated junction field effect transistor, having a controlled electrode and first and second controlling electrodes, said controlled electrode being the gate electrode of said junction field effect transistor; a resistor having a fixed value of resistance coupled to said controlled electrode of said transistor; at least one word line and at least one bit line connected to said memory cell; said controlled electrode being held at one of two DC stable potential levels, indicative of one of two binary states, as a function of voltage levels applied by means of the word line and the bit line; and a variable impedance means integrated in a channel adjacent to said controlled electrode, the impedance of said variable impedance means being altered by the controlled electrode, which is operable to pinch off said channel responsive to a set of voltage levels applied by means of the word line and the bit line, such that when said variable impedance is at a low impedance the memory cell is sustained in a first binary state, and when said variable impedance is at a high impedance the memory cell is sustained in a second binary state.
Claim 3
Dependent Claim
75 words
A memory cell as defined in claim 1, in which there is provided a conductive path including said variable impedance means and a potential source; said conductive path also including said resistor having a fixed value of resistance, and means for connecting to said potential source; the resistor of fixed value being connected to a node common to said variable impedance means, the other end of said variable impedance means being connected to reference potential.
Claim 4
Dependent Claim
34 words
A method cell as defined in claim 2, in which the potential level at said node is effective to hold the controlled electrode at a potential which keeps the cell in the selected state.
Claim 5
Dependent Claim
207 words
A DC-stable integrated memory array having a plurality of memory cells, each memory cell comprising: an integrated junction field effect transistor, having a controlled electrode and first and second controlling electrodes, said controlled electrode being the gate electrode of said junction field effect transistor; a resistor having a fixed value of resistance coupled to said controlled electrode of said transistor; at least one word line and at least one bit line connected to said memory cell; said controlled electrode being held at one of two DC stable potential levels, indicative of one of two binary states, as a function of voltage levels applied by means of the word line and the bit line; and a variable impedance means integrated in a channel adjacent to said controlled electrode, the impedance of said variable impedance means being altered by the controlled electrode, which is operable to pinch off said channel responsive to a set of voltage levels applied by means of the word line and the bit line, such that when said variable impedance is at a low impedance the memory cell is sustained in a first binary state, and when said variable impedance is at a high impedance the memory cell is sustained in a second binary state.
Claim 6
Dependent Claim
207 words
A DC-stable integrated memory array having a plurality of memory cells, each memory cell comprising: an integrated junction field effect transistor, having a controlled electrode and first and second controlling electrodes, said controlled electrode being the gate electrode of said junction field effect transistor; a resistor having a fixed value of resistance coupled to said controlled electrode of said transistor; at least one word line and at least one bit line connected to said memory cell; said controlled electrode being held at one of two DC stable potential levels, indicative of one of two binary states, as a function of voltage levels applied by means of the word line and the bit line; and a variable impedance means integrated in a channel adjacent to said controlled electrode, the impedance of said variable impedance means being altered by the controlled electrode, which is operable to pinch off said channel responsive to a set of voltage levels applied by means of the word line and the bit line, such that when said variable impedance is at a low impedance the memory cell is sustained in a first binary state, and when said variable impedance is at a high impedance the memory cell is sustained in a second binary state.
Claim 7
Dependent Claim
80 words
A memory array as defined in claim 4, in which each of the memory cells is provided with a conductive path including said variable impedance means and a potential source; said conductive path also including said resistor having a fixed value of resistance, and means for connecting to said potential source; the resistor of fixed value being connected to a node common to said variable impedance means, the other end of said variable impedance means being connected to reference potential.
Claim 8
Dependent Claim
34 words
A memory array as defined in claim 5, in which the potential level of said node is effective to hold the controlled electrode at a potential which keeps the cell in the selected state.
Claim 9
Dependent Claim
217 words
A DC-stable, integrated memory array having a plurality of memory cells, each memory cell comprising: a power supply terminal for providing a fixed potential level; an integrated junction field effect transistor, having a controlled electrode and first and second controlling electrodes, said controlled electrode being the gate electrode of said junction field effect transistor; a resistor having a fixed value of resistance coupled to said controlled electrode of said transistor; at least one word line and at least one bit line connected to said memory cell; said controlled electrode being held at one of two DC stable potential levels, indicative of one of two binary states, as a function of voltage levels applied by means of the word line and the bit line; and a variable impedance means integrated in a channel adjacent to said controlled electrode, the impedance of said variable impedance means being altered by the controlled electrode, which is operable to pinch off said channel responsive to a set of voltage levels applied by means of the word line and the bit line, such that when said variable impedance is at a low impedance the memory cell is sustained in a first binary state, and when said variable impedance is at a high impedance the memory cell is sustained in a second binary state.
Claim 10
Dependent Claim
217 words
A DC-stable, integrated memory array having a plurality of memory cells, each memory cell comprising: a power supply terminal for providing a fixed potential level; an integrated junction field effect transistor, having a controlled electrode and first and second controlling electrodes, said controlled electrode being the gate electrode of said junction field effect transistor; a resistor having a fixed value of resistance coupled to said controlled electrode of said transistor; at least one word line and at least one bit line connected to said memory cell; said controlled electrode being held at one of two DC stable potential levels, indicative of one of two binary states, as a function of voltage levels applied by means of the word line and the bit line; and a variable impedance means integrated in a channel adjacent to said controlled electrode, the impedance of said variable impedance means being altered by the controlled electrode, which is operable to pinch off said channel responsive to a set of voltage levels applied by means of the word line and the bit line, such that when said variable impedance is at a low impedance the memory cell is sustained in a first binary state, and when said variable impedance is at a high impedance the memory cell is sustained in a second binary state.
Claim 11
Dependent Claim
85 words
A memory array as defined in claim 7, in which in each of said memory cells there is provided a conductive path including said variable impedance means, said conductive path also including said power supply terminal, said resistor having a fixed value of resistance, and means for connecting said resistor to said power supply terminal; the resistor of fixed value being connected to a node common to said variable impedance means, the other end of said variable impedance means being connected in said reference potential.
Claim 12
Dependent Claim
34 words
A memory array as defined in claim 8, in which the potential level at said node is effective to hold the controlled electrode at a potential which keeps the cell in the selected state.
Claim 13
Dependent Claim
204 words
A DC-stable memory cell comprising: an integrated transistor having a controlled electrode and first and second controlling electrodes; a resistor having a fixed value of resistance coupled to said controlled electrode of said transistor; at least one word line and at least one bit line connected to said memory cell; said controlled electrode being held at one of two DC stable potential levels, indicative of one of two binary states, as a function of voltage levels applied by means of the word line and the bit line; and a variable impedance means integrated in a channel adjacent to and immediately below said controlled electrode, the impedance of said variable impedance means being altered by the controlled electrode, which is operable to pinch off said channel responsive to a set of voltage levels applied by means of the word line and the bit line, such that when said variable impedance is at a low impedance the memory cell is sustained in a first binary state and when said variable impedance is at a high impedance the memory cell is sustained in a first binary state and when said variable impedance is at a high impedance the memory cell is sustained in a second binary state.
Claim 14
Dependent Claim
204 words
A DC-stable memory cell comprising: an integrated transistor having a controlled electrode and first and second controlling electrodes; a resistor having a fixed value of resistance coupled to said controlled electrode of said transistor; at least one word line and at least one bit line connected to said memory cell; said controlled electrode being held at one of two DC stable potential levels, indicative of one of two binary states, as a function of voltage levels applied by means of the word line and the bit line; and a variable impedance means integrated in a channel adjacent to and immediately below said controlled electrode, the impedance of said variable impedance means being altered by the controlled electrode, which is operable to pinch off said channel responsive to a set of voltage levels applied by means of the word line and the bit line, such that when said variable impedance is at a low impedance the memory cell is sustained in a first binary state and when said variable impedance is at a high impedance the memory cell is sustained in a first binary state and when said variable impedance is at a high impedance the memory cell is sustained in a second binary state.
Claim 15
Dependent Claim
244 words
A DC-stable, integrated memory array having a plurality of memory cells, each memory cell comprising: a power supply terminal for providing a fixed potential level; an integrated transistor having a controlled electrode and first and second controlling electrodes; a resistor having a fixed value of resistance and coupled between said power supply terminal and said controlled electrode of said transistor; at least one word line and at least one bit line connected to said memory array; the first controlling electrode of the transistor being coupled to the word line of said memory array; the second controlling electrode of said transistor being coupled to the bit line of said memory array; said controlled electrode being held at one of two DC stable potential levels, indicative of one of two binary states; as a function of voltage levels applied by means of the word line and the bit line; and a variable impedance means integrated in a channel adjacent to and immediately below said controlled electrode, the impedance of said variable impedance means being altered by the controlled electrode, which is operable to pinch off said channel responsive to a set of voltage levels applied by means of the word line and the bit line, such that when said variable impedance is at a low impedance the memory cell is sustained in a first binary state and when said variable impedance is at a high impedance the memory cell is sustained in a second binary state.
Claim 16
Dependent Claim
244 words
A DC-stable, integrated memory array having a plurality of memory cells, each memory cell comprising: a power supply terminal for providing a fixed potential level; an integrated transistor having a controlled electrode and first and second controlling electrodes; a resistor having a fixed value of resistance and coupled between said power supply terminal and said controlled electrode of said transistor; at least one word line and at least one bit line connected to said memory array; the first controlling electrode of the transistor being coupled to the word line of said memory array; the second controlling electrode of said transistor being coupled to the bit line of said memory array; said controlled electrode being held at one of two DC stable potential levels, indicative of one of two binary states; as a function of voltage levels applied by means of the word line and the bit line; and a variable impedance means integrated in a channel adjacent to and immediately below said controlled electrode, the impedance of said variable impedance means being altered by the controlled electrode, which is operable to pinch off said channel responsive to a set of voltage levels applied by means of the word line and the bit line, such that when said variable impedance is at a low impedance the memory cell is sustained in a first binary state and when said variable impedance is at a high impedance the memory cell is sustained in a second binary state.
References Cited (Backward Citations)
US3914749A
Cited
US4124111A
Cited
US4070653A
Cited
US4092735A
Cited
US4142112A
Cited
US4139785A
Cited
US4352997A
Cited
US4122545A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-13 | 1987-08-15 | 1988-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-13 | 1991-08-15 | 1992-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-13 | 1995-08-15 | 1996-02-14 | $7700.00 | Window Closed / Lapsed |