US4122545A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory array of inversion controlled switches
Assignee: Unisys Corp
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Filing: 1978-01-03
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Granted: 1978-10-24
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Expires: 1998-01-03
Abstract
Abstract The present invention relates to a memory circuit including an array of inversion controlled switches arranged in an arbitrary number of rows and columns. Each inversion controlled switch is provided with emitter, base and collector terminals, and is characterized by first and second impedance states between its emitter and collector terminals. The memory circuit further includes voltage means coupled with the inversion controlled switches of the array for applying a selectively controllable voltage across the emitter and collector terminals of these switches in selected ones of the rows; a plurality of rectifier means each coupled with the base terminal of a respective inversion controlled switch; current means coupled with the rectifier means for applying a current level to the base terminals of the inversion controlled switches in selected ones of the columns through the rectifier means; and data sensing means coupled with the inversion controlled switches in individual ones of the columns for sensing the impedance state of a selected one of the switches in a respective one of the columns.
Inventors
- 👤 Robert J. Lodi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:05
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6221; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/35; G11C11/39
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
158 words
A memory circuit, comprising: an array of inversion controlled switch means of N rows by M columns, each said switch means having emitter, base and collector terminals, and characerized by first and second discrete impedance states between the emitter and collector terminals thereof; voltage means coupled with said switch means for applying a selectably controllable voltage level across the emitter and collector terminals of said switch means in selected ones of said rows thereof; a plurality of rectifier means each coupled with the base terminal of a respective switch means; current means coupled with said rectifier means for applying a selectably controllable current level to the base terminals of said switch means in selected ones of said columns through said rectifier means; and data sensing means coupled with said switch means in individual ones of said columns thereof for sensing the impedance state of a selected one of said switch means in a respective one of said columns.
Claim 2
Dependent Claim
158 words
A memory circuit, comprising: an array of inversion controlled switch means of N rows by M columns, each said switch means having emitter, base and collector terminals, and characerized by first and second discrete impedance states between the emitter and collector terminals thereof; voltage means coupled with said switch means for applying a selectably controllable voltage level across the emitter and collector terminals of said switch means in selected ones of said rows thereof; a plurality of rectifier means each coupled with the base terminal of a respective switch means; current means coupled with said rectifier means for applying a selectably controllable current level to the base terminals of said switch means in selected ones of said columns through said rectifier means; and data sensing means coupled with said switch means in individual ones of said columns thereof for sensing the impedance state of a selected one of said switch means in a respective one of said columns.
Claim 3
Dependent Claim
69 words
The memory circuit of claim 1, in which each said rectifying means is provided with a first terminal and a second terminal, the first terminal thereof being connected to the base terminal of said respective switch means and the second terminal thereof being connected to the second terminals of the others of said rectifying means in the corresponding column of said respective switch means and with said current means.
Claim 4
Dependent Claim
136 words
The memory circuit of claim 2 in which said data sensing means comprises a plurality of data sensing amplifiers each having an input and an output, and the emitter terminal of each said switch means is connected with the emitter terminals of the others of said switch means in the corresponding column thereof and to the input of a respective data sensing amplifier such that the application of a predetermined read voltage level across the emitter and collector terminals of said switch means in a selected one of said rows by said voltage means will provide a data output signal at the output of each said data sensing amplifier indicative of the impedance state of the switch means in the column corresponding to the respective data sensing amplifier and in the selected one of said rows.
Claim 5
Dependent Claim
60 words
The memory circuit of claim 2, further comprising a plurality of impedance means each coupled with the collector terminal of a respective one of said switch means, said voltage means being coupled with the collector terminals of said switch means in respective ones of said rows through said plurality of impedance means to apply a selectably controllable voltage level thereto.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-23 | 1982-04-24 | 1982-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-23 | 1986-04-24 | 1986-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-23 | 1990-04-24 | 1990-10-24 | $7700.00 | Window Closed / Lapsed |