D.C. stable single device memory cell

Claim 2

A transistor memory cell comprising: an emitter, a base and a collector; said base including an intrinsic region and first and second extrinsic regions adjacent said intrinsic region; means for applying potentials to said emitter, collector and at least said first extrinsic region; said intrinsic region having an area which is substantially coextensive with said emitter, and having a relatively low doping level such that the application of reverse biases to said emitter and collector with respect to said base causes said intrinsic base region to be pinched off; whereby the potentials at said emitter and at second extrinsic base region may assume two stable levels indicative of two stable memory conditions.

Claim 3

A memory cell as in claim 1 further comprising: isolation means contiguous to the sides of said intrinsic region, thereby eliminating lateral conducting paths from said intrinsic region.

Claim 4

A memory cell as in claim 2 wherein said isolation means comprises silicon dioxide.

Claim 5

A memory cell as in claim 2 wherein said isolation means is also contiguous to the sides of said first and second extrinsic regions.

Claim 6

A memory cell as in claim 1 wherein the doping level of said intrinsic region is around 5 X 1015 atoms/cm3 to 1 X 1016 atoms/cm3.

Claim 7

A memory cell as in claim 5 wherein the ratio of the length of the emitter between extrinsic regions is around 5 times greater than the emitter width, thereby ensuring a substantial difference between said two stable potential levels of said memory cell.

Claim 8

A method for operating the transistor memory cell defined in claim 1 as a bistable device comprising the steps of: reverse-biasing said emitter and collector with respect to said base region, thereby causing said intrinsic base region to be pinched off and the potential in said second extrinsic base region to be raised; removing the source of said reverse-bias potential from said emitter, thereby raising the potential at said emitter to a first stable state indicative of a first stable memory condition; and applying a potential to said emitter which is below the level necessary to sustain said first stable state thereby lowering the potential at said emitter to a second stable memory condition.

Claim 9

A memory cell as in claim 1 further comprising: means for applying a potential to said second extrinsic region.

Claim 10

A method for non-destructively sensing said stable memory conditions in the memory cell defined in claim 8 comprising the steps of: applying a source of voltage through a series resistance to said potential-applying means of said second extrinsic region; the value of said voltage being at least equal to the higher value of potential which may exist at said second extrinsic base region; the value of said resistance being sufficiently high so as to prevent said voltage from affecting the lower value of potential which may exist at said second extrinsic base region; and monitoring the current which flows from said source of voltage through said second extrinsic base region, the presence or absence of significant current flow being indicative of said lower or higher value of potential, respectively.

Claim 11

A single device D.C.-stable memory cell comprising: a bipolar transistor of the planar type including an intrinsic base region below, and first and second extrinsic base regions adjacent to the sides oF the emitter; the area of said intrinsic region being substantially coextensive with the area of said emitter; means for applying bias potentials to the emitter, collector and said first extrinsic base regions; said intrinsic base region having a relatively low doping level such that the application of reverse bias potentials to said emitter and collector with respect to said base region causes said intrinsic base region to be pinched off, whereby the potentials at said emitter and said second extrinsic base region may assume two stable levels indicative of two stable memory conditions.

Claim 12

A single device D.C.-stable memory cell comprising: a bipolar transistor of the planar type including an intrinsic base region below, and first and second extrinsic base regions adjacent to the sides oF the emitter; the area of said intrinsic region being substantially coextensive with the area of said emitter; means for applying bias potentials to the emitter, collector and said first extrinsic base regions; said intrinsic base region having a relatively low doping level such that the application of reverse bias potentials to said emitter and collector with respect to said base region causes said intrinsic base region to be pinched off, whereby the potentials at said emitter and said second extrinsic base region may assume two stable levels indicative of two stable memory conditions.

Claim 13

A memory cell as in claim 10 further comprising: isolation means contiguous to the side of said intrinsic region, thereby eliminating lateral conducting paths from said intrinsic region.

Claim 14

A memory cell as in claim 11 wherein said isolation means comprises silicon dioxide.

Claim 15

A memory cell as in claim 11 wherein said isolation means is also contiguous to the sides of said first and second extrinsic regions.

Claim 16

A memory cell as in claim 10 wherein the doping level of said intrinsic region is around 5 X 1015 atoms/cm3 to 1 X 1016 atoms/cm3.

Claim 17

A memory cell as in claim 14 wherein the ratio of the length of the emitter between extrinsic regions is around 5 times greater than the emitter width, thereby ensuring a substantial difference between said two stable potential levels of said memory cell.

Claim 18

A method for operating the memory cell defined in claim 10 comprising the steps of: reverse-biasing the emitter and collector of said bipolar transistor with respect to said base region, thereby causing said intrinsic base region to be pinched off and the potential in said second extrinsic base region to be raised; removing the source of said reverse-bias potential from said emitter, thereby raising the potential at said emitter to a first stable state indicative of a first stable memory condition; and applying a potential to said emitter which is below the level necessary to sustain said first stable state, thereby lowering the potential at said emitter to a second stable memory condition.

Claim 19

A memory cell as in claim 10 further comprising: means for applying a potential to said second extrinsic region.

Claim 20

A method for non-destructively sensing said stable memory conditions in the memory cell defined in claim 17 comprising the steps of: applying a source of voltage through a series resistance to said potential-applying means of said second extrinsic region; the value of said voltage being at least equal to the higher value of potential which may exist at said second extrinsic base region; the value of said resistance being sufficiently high so as to prevent said voltage from affecting the lower value of potential which may exist at said second extrinsic base region; and monitoring the current which flows from said source of voltage through said second extrinsic base region, the presence or absence of significant current flow being indicative of said lower or higher value of potential, respectively.

Claim 21

A single device, D.C. stable memory cell comprising: a bipolar transistor of the planar type including an intrinsic base region below, and first and second extrinsic base regions adjacent to the sides of the emitter; isolation means contiguous to the sides of said intrinsic base region and said emitter to substantially equalize the areas of said emitter and said intrinsic base region at their interface; the length of the emitter between said extrinsic base regions being substantially greater than the width of said emitter; means for applying bias potentials to the emitter, collector and said first extrinsic base regions; said intrinsic base region having a relatively low doping level such that the application of reverse bias potentials to said emitter and collector with respect to said base region causes said intrinsic base region to Be pinched off, whereby the potentials at said emitter and said second extrinsic base region may assume two stable levels indicative of two stable memory conditions.

Claim 22

A single device, D.C. stable memory cell comprising: a bipolar transistor of the planar type including an intrinsic base region below, and first and second extrinsic base regions adjacent to the sides of the emitter; isolation means contiguous to the sides of said intrinsic base region and said emitter to substantially equalize the areas of said emitter and said intrinsic base region at their interface; the length of the emitter between said extrinsic base regions being substantially greater than the width of said emitter; means for applying bias potentials to the emitter, collector and said first extrinsic base regions; said intrinsic base region having a relatively low doping level such that the application of reverse bias potentials to said emitter and collector with respect to said base region causes said intrinsic base region to Be pinched off, whereby the potentials at said emitter and said second extrinsic base region may assume two stable levels indicative of two stable memory conditions.

Claim 23

A memory cell as in claim 19 wherein: the doping level of said intrinsic region is around 5 X 1015 atoms/cm3 to 1 X 1016 atoms/cm3; and said emitter lenght-to-width ratio is around 5:1.

Claim 24

A memory cell as in claim 20 further comprising: means for applying a voltage source to said second extrinsic base region whereby the contents of said cell may be sensed non-destructively.