US5463234A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed semiconductor gain memory cell with minimal area occupancy
Assignee: Toshiba Corp
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Filing: 1995-03-17
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Granted: 1995-10-31
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Expires: 2015-03-17
Abstract
Abstract A semiconductor memory device, in particular a dynamic random access memory cell which realizes a high speed thereof and presenting a superior controllability. The dynamic random access memory (DRAM) cell includes: a first transistor; a second transistor, electrically connected in series to the first transistor, for storing an electric charge, the second transistor including a portion for erasing the charge stored at the second transistor, wherein the first transistor and the second transistor are electrically connected between a power line and a bit line; and a diode electrically connected between the first transistor and the second transistor. Alternatively, the present invention can be realized with three transistors where the memory cell includes: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series at a connecting node therebetween; and a third transistor provided between a gate of the first transistor and the connecting node, wherein a gate of the second transistor and a gate of the third transistor are commonly connected to the word line.
Inventors
- 👤 Akira Toriumi
- 👤 Naoyuki Shigyo
- 👤 Tetsunori Wada
- 👤 Hiroyoshi Tanimoto
- 👤 Kazuya Ohuchi
- 👤 Makoto Yoshimi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:35
CPC Classifications
H; H10; H10B; H10B12/00; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
147 words
A dynamic random access memory (DRAM) cell equipped with a power supply line, a bit line and a word line therein, the memory cell comprising: first transistor, having a gate, a source and a drain; a second transistor, for storing an electric charge; said second transistor having a first gate for erasing the charge stored at the second transistor, a second gate, a source and a drain; and a diode having first and second electrodes, wherein said drain of said first transistor is connected to said source of said second transistor and said first electrode of said diode; said first and second gates are commonly connected to said second electrode of said diode; said source of said first transistor, said gate of said first transistor and said drain of said second transistor are connected to said bit line, said word line, and said power supply line, respectively.
Claim 2
Dependent Claim
147 words
A dynamic random access memory (DRAM) cell equipped with a power supply line, a bit line and a word line therein, the memory cell comprising: first transistor, having a gate, a source and a drain; a second transistor, for storing an electric charge; said second transistor having a first gate for erasing the charge stored at the second transistor, a second gate, a source and a drain; and a diode having first and second electrodes, wherein said drain of said first transistor is connected to said source of said second transistor and said first electrode of said diode; said first and second gates are commonly connected to said second electrode of said diode; said source of said first transistor, said gate of said first transistor and said drain of said second transistor are connected to said bit line, said word line, and said power supply line, respectively.
Claim 3
Dependent Claim
20 words
The memory cell of claim 1, wherein said first gate is configured at a source side of the second transistor.
Claim 4
Dependent Claim
55 words
The memory cell of claim 1, wherein said first gate includes a first gate insulator and a first gate electrode formed on the first gate insulator, and the second gate includes a second gate insulator whose thickness is thicker than the first gate insulator and a second gate electrode formed on the second gate insulator.
Claim 5
Dependent Claim
34 words
The memory cell of claim 1, wherein said first and second gates include barriers for a tunnel current, wherein the barrier height of said first gate is lower than that of said second gate.
Claim 6
Dependent Claim
13 words
The memory cell of claim 1, wherein the diode is a Schottky diode.
Claim 7
Dependent Claim
96 words
A dynamic random access memory (DRAM) cell equipped with a power source line, a bit line and a word line therein, the memory cell comprising: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series at a connecting node therebetween; and a third transistor provided between a gate of the first transistor and the connecting node, wherein a gate of the second transistor and a gate of the third transistor are commonly connected to the word line.
Claim 8
Dependent Claim
96 words
A dynamic random access memory (DRAM) cell equipped with a power source line, a bit line and a word line therein, the memory cell comprising: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series at a connecting node therebetween; and a third transistor provided between a gate of the first transistor and the connecting node, wherein a gate of the second transistor and a gate of the third transistor are commonly connected to the word line.
Claim 9
Dependent Claim
91 words
A dynamic random access memory (DRAM) cell equipped with a power supply line, a bit line and a word line therein, the DRAM cell comprising: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series; and a third transistor provided between a gate of the first transistor and the bit line, wherein a gate of the second transistor and a gate of the third transistor are commonly connected to the word line.
Claim 10
Dependent Claim
91 words
A dynamic random access memory (DRAM) cell equipped with a power supply line, a bit line and a word line therein, the DRAM cell comprising: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series; and a third transistor provided between a gate of the first transistor and the bit line, wherein a gate of the second transistor and a gate of the third transistor are commonly connected to the word line.
Claim 11
Dependent Claim
96 words
A dynamic random access memory (DRAM) cell equipped with a power source line, a bit line and a word line therein, the memory cell comprising: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series at a connecting node therebetween; and a third transistor provided between a gate of the second transistor and the connecting node, wherein a gate of the first transistor and a gate of the third transistor are commonly connected to the word line.
Claim 12
Dependent Claim
96 words
A dynamic random access memory (DRAM) cell equipped with a power source line, a bit line and a word line therein, the memory cell comprising: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series at a connecting node therebetween; and a third transistor provided between a gate of the second transistor and the connecting node, wherein a gate of the first transistor and a gate of the third transistor are commonly connected to the word line.
Claim 13
Dependent Claim
91 words
A dynamic random access memory (DRAM) cell equipped with a power supply line, a bit line and a word line therein, the DRAM cell comprising: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series; and a third transistor provided between a gate of the second transistor and the bit line, wherein a gate of the first transistor and a gate of the third transistor are commonly connected to the word line.
Claim 14
Dependent Claim
91 words
A dynamic random access memory (DRAM) cell equipped with a power supply line, a bit line and a word line therein, the DRAM cell comprising: a first transistor and a second transistor provided between the power line and the bit line in a manner that the first and second transistors are connected in series; and a third transistor provided between a gate of the second transistor and the bit line, wherein a gate of the first transistor and a gate of the third transistor are commonly connected to the word line.
Claim 15
Dependent Claim
33 words
The memory cell of claims 6, 7, 8 or 9, wherein a threshold voltage of the second transistor is smaller than that of the third transistor in terms of an absolute value thereof.
Claim 16
Dependent Claim
50 words
The memory cell of claim 6, 7, 8, or 9, further comprising a fourth transistor whose gate is commonly connected to a gate of the first transistor, whose source is connected to a drain of the first transistor and whose drain is connected to a source of the third transistor.
Claim 17
Dependent Claim
21 words
The memory cell of claims 1, 6, 7, 8 or 9, wherein the transistors are of MOS, MIS or MES type.
Claim 18
Dependent Claim
87 words
The memory cell of claims 6, 7, 8 or 9, wherein there is formed a trench on a substrate, there are formed the first and second transistors on sidewalls of the trench, there is formed the third transistor on a semiconductor film filled in the trench, and the memory cell is characterized in that a gate of the second transistor is formed on the semiconductor film filled in the trench, and the gate 15 of the second transistor simultaneously serves as a gate of the third transistor.
Claim 19
Dependent Claim
75 words
The memory cell of claims 6, 7, 8 or 9, wherein: there are formed first and second trenches, interposing a thin insulating film therebetween, which acts as a gate insulator for said third transistor; and the memory cell is characterized in that the gate insulator of the first transistor is formed on the sidewall of the first trench, and the gate insulator of the second transistor is formed on the sidewall of the second trench.
Claim 20
Dependent Claim
62 words
The memory cell of claims 6, 7, 8 or 9, wherein there are formed the first and second transistors on a substrate; and there is formed the third transistor formed on a semiconductor film deposited over a region extending over both the first and second transistors, a channel region of the third transistor being formed adjacent a gate of the second transistor.
Claim 21
Dependent Claim
27 words
The memory cell of claim 15, wherein the semiconductor film on which there is formed the third transistor simultaneously serves as a gate of the first transistor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-30 | 1999-05-01 | 1999-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-30 | 2003-05-01 | 2003-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-30 | 2007-05-01 | 2007-10-31 | $7700.00 | Window Closed / Lapsed |