Method of making trench MOS-gated device with a minimum number of masks

Claim 1

A method for fabricating an array of insulated-gate field-effect transistors, comprising the steps of: (a.) providing substantially monocrystalline semiconductor material, including a first portion having a first conductivity type, a second portion which overlies said first portion and has a second conductivity type, and a third portion which overlies said second portion and has said first conductivity type; and forming oxidation-resistant material on said semiconductor material; (b.) etching both said oxidation-resistant material and said semiconductor material thereunder in a common pattern to form trenches in said semiconductor material; (c.) forming an insulating layer on sidewalls of said trenches; (d.) conformally depositing an oxidizable conductor overall, to a depth which fills said trenches, and etching back said oxidizable conductor to leave portions thereof in said trenches which are capacitively coupled to sidewall portions of said trenches; (e.) oxidizing said oxidizable conductor to form a thick insulating layer thereon; (f.) removing said oxidation-resistant material and substantially all of said third portion of semiconductor material from desired deep body locations, and introducing an additional concentration of dopants of said second conductivity type; and (g.) making contact to exposed portions of said third and second portions; whereby said third and second portions provide source and channel regions, respectively, of a field-effect transistor which is gated by said oxidizable conductor material within said trench.

Claim 2

A method for fabricating an array of insulated-gate field-effect transistors, comprising the steps of: (a.) providing substantially monocrystalline semiconductor material, including a first portion having a first conductivity type, a second portion which overlies said first portion and has a second conductivity type, and a third portion which overlies said second portion and has said first conductivity type; and forming oxidation-resistant material on said semiconductor material; (b.) etching both said oxidation-resistant material and said semiconductor material thereunder in a common pattern to form trenches in said semiconductor material; (c.) forming an insulating layer on sidewalls of said trenches; (d.) conformally depositing an oxidizable conductor overall, to a depth which fills said trenches, and etching back said oxidizable conductor to leave portions thereof in said trenches which are capacitively coupled to sidewall portions of said trenches; (e.) oxidizing said oxidizable conductor to form a thick insulating layer thereon; (f.) removing said oxidation-resistant material and substantially all of said third portion of semiconductor material from desired deep body locations, and introducing an additional concentration of dopants of said second conductivity type; and (g.) making contact to exposed portions of said third and second portions; whereby said third and second portions provide source and channel regions, respectively, of a field-effect transistor which is gated by said oxidizable conductor material within said trench.

Claim 10

A method for fabricating an array of insulated-gate field-effect transistors, comprising the steps of: (a.) providing substantially monocrystalline semiconductor material, including a substrate portion having a first conductivity type and an overlying portion having a second conductivity type; (b.) forming islands of oxidation-resistant material on said semiconductor material; (c.) etching said semiconductor material, where exposed by said islands, to remove said overlying portion thereof while also partially undercutting said islands to create mesas in said semiconductor material; (d.) implanting said semiconductor material where exposed by said islands, to create body regions of said second conductivity type in said substrate portion; (e.) removing said islands of oxidation-resistant material, and etching trenches into said semiconductor material in locations of said mesas; (f.) forming insulated gates which are capacitively coupled to sidewall portions of said trenches; (g.) forming source diffusions of a first conductivity type in remaining portions of said overlying portion adjacent to at least some ones of said trenches; and (h.) making contact to said source diffusions and body regions.

Claim 11

A method for fabricating an array of insulated-gate field-effect transistors, comprising the steps of: (a.) providing substantially monocrystalline semiconductor material, including a substrate portion having a first conductivity type and an overlying portion having a second conductivity type; (b.) forming islands of oxidation-resistant material on said semiconductor material; (c.) etching said semiconductor material, where exposed by said islands, to remove said overlying portion thereof while also partially undercutting said islands to create mesas in said semiconductor material; (d.) implanting said semiconductor material where exposed by said islands, to create body regions of said second conductivity type in said substrate portion; (e.) removing said islands of oxidation-resistant material, and etching trenches into said semiconductor material in locations of said mesas; (f.) forming insulated gates which are capacitively coupled to sidewall portions of said trenches; (g.) forming source diffusions of a first conductivity type in remaining portions of said overlying portion adjacent to at least some ones of said trenches; and (h.) making contact to said source diffusions and body regions.

Claim 16

A method for fabricating an array of insulated-gate field-effect transistors, comprising the steps of: (a.) providing substantially monocrystalline semiconductor material, including a substrate portion having a first conductivity type and an overlying portion having a second conductivity type; (b.) forming trenches in said semiconductor material, extending through said overlying portion thereof into said substrate portion; (c.) forming a thin film layer of an oxidizable conductor which extends into said trenches to provide capacitive coupling to sidewall portions of said trenches; (d.) oxidizing said oxidizable conductor to form a thick oxide thereon; (e.) removing oxide overall, to a depth which is not sufficient to remove all oxide from said oxidizable conductor; (f.) implanting dopants of a first conductivity type to form source diffusions in remaining portions of said overlying portion adjacent to at least some ones of said trenches; and (g.) making contact to said source diffusions and body regions.

Claim 17

A method for fabricating an array of insulated-gate field-effect transistors, comprising the steps of: (a.) providing substantially monocrystalline semiconductor material, including a substrate portion having a first conductivity type and an overlying portion having a second conductivity type; (b.) forming trenches in said semiconductor material, extending through said overlying portion thereof into said substrate portion; (c.) forming a thin film layer of an oxidizable conductor which extends into said trenches to provide capacitive coupling to sidewall portions of said trenches; (d.) oxidizing said oxidizable conductor to form a thick oxide thereon; (e.) removing oxide overall, to a depth which is not sufficient to remove all oxide from said oxidizable conductor; (f.) implanting dopants of a first conductivity type to form source diffusions in remaining portions of said overlying portion adjacent to at least some ones of said trenches; and (g.) making contact to said source diffusions and body regions.

Claim 23

A method for fabricating an array of insulated-gate field-effect transistors, comprising the steps of: (a.) providing substantially monocrystalline semiconductor material, including a substrate portion having a first conductivity type and an overlying portion having a second conductivity type; (b.) forming islands of oxidation-resistant material on said semiconductor material; (c.) etching said semiconductor material, where exposed by said islands, to remove said overlying portion thereof while also partially undercutting said islands to create mesas in said semiconductor material; (d.) implanting said semiconductor material where exposed by said islands, to create body regions of said second conductivity type in said substrate portion; (e.) removing said islands of oxidation-resistant material, and etching trenches into said semiconductor material in locations of said mesas; (f.) forming insulated conductive gates which are capacitively coupled to sidewall portions of said trenches; (g.) forming a thin film layer of an oxidizable conductor which extends into said trenches to provide capacitive coupling to sidewall portions of said trenches; (h.) oxidizing said oxidizable conductor to form a thick oxide thereon; (i.) removing oxide overall, to a depth which is not sufficient to remove all oxide from said oxidizable conductor; (j.) implanting dopants of a first conductivity type to form source diffusions in remaining portions of said overlying portion adjacent to at least some ones of said trenches; and (k.) making contact to said source diffusions and body regions.

Claim 24

A method for fabricating an array of insulated-gate field-effect transistors, comprising the steps of: (a.) providing substantially monocrystalline semiconductor material, including a substrate portion having a first conductivity type and an overlying portion having a second conductivity type; (b.) forming islands of oxidation-resistant material on said semiconductor material; (c.) etching said semiconductor material, where exposed by said islands, to remove said overlying portion thereof while also partially undercutting said islands to create mesas in said semiconductor material; (d.) implanting said semiconductor material where exposed by said islands, to create body regions of said second conductivity type in said substrate portion; (e.) removing said islands of oxidation-resistant material, and etching trenches into said semiconductor material in locations of said mesas; (f.) forming insulated conductive gates which are capacitively coupled to sidewall portions of said trenches; (g.) forming a thin film layer of an oxidizable conductor which extends into said trenches to provide capacitive coupling to sidewall portions of said trenches; (h.) oxidizing said oxidizable conductor to form a thick oxide thereon; (i.) removing oxide overall, to a depth which is not sufficient to remove all oxide from said oxidizable conductor; (j.) implanting dopants of a first conductivity type to form source diffusions in remaining portions of said overlying portion adjacent to at least some ones of said trenches; and (k.) making contact to said source diffusions and body regions.