Vertical DMOS transistor fabrication process

Claim 1

A process for fabricating a vertical DMOS transistor, having source, drain, gate and body regions, comprising the steps: providing a high conductivity semiconductor substrate wafer having a first conductivity type and a similar conductivity type epitaxial layer thereon; forming an opposite conductivity type body region extending part way through said epitaxial layer; forming a heavily doped opposite conductivity type region surrounding said body region to define said DMOS transistor and to provide a deep body contact; forming a refractory metal layer over said body region to provide a contact thereto; forming a gate region within said body region by etching a trench in said epitaxial layer to completely penetrate said body region, forming a gate oxide on the walls of said trench, filling said trench with doped polysilicon and removing the excess polysilicon to leave said trench filled with conductive polysilicon to provide said gate electrode of said DMOS transistor; and forming contacts to said refractory metal, said conductive polysilicon, said deep body contact region and said substrate wafer, wherein said refractory metal acts as said source of said DMOS transistor, and wherein said refractory metal also forms an ohmic connection to said deep body contact region.