Insulated gate type field-effect transistor

Abstract

Abstract PURPOSE:To decrease the concentration of an electric field and increase dielectric resistance by a mechanism wherein a gate SiO2 film is formed on a wall surface of a concave section made up to a drain region when preparing a longitudinal MOSFET, and a region having the extremely low concentration of impurities is previously formed into the drain region at a nose of the concave section. CONSTITUTION:An N<-> layer 202 functioning as the second drain region is grown on an N<+> type semiconductor substrate 201 serving as the first drain region in an epitaxial shape, a P type layer 203 is formed on the layer 202, and an N<+> type source region 204 is made up into the layer 203 in a diffusion shape. A groove section 205, which is located at the central section of the region 204 and a nose thereof is put into the layer 202, is bored, the wall surface is coated with an Al gate electrode 207 through a gate SiO2 film 206, a window is opened to the SiO2 film formed on an exposed surface of the layer 203 and a source electrode 208 contacting with the region 204 is made up, and a drain electrode 209 is built up on the back of the substrate 201, thus forming an FET. An N(-)(-) type region 210 is previously made up into the layer 202 in response to the nose of the groove section 205 in this constitution, the distribution of potential here is eased, the concentration of an electric field is decreased, and the FET is made resistent to high voltage.

Inventors

• 👤 Kuniharu Kato
• 👤 Hitoshi Nagano
• 👤 Yuki Shimada
• 👤 Shusaburo Imai
• 👤 Kenji Hideshima
• 👤 Hisashi Haneda

Bibliographic Details