Patent US5754801A successfully refreshed from Google Patents.
US5754801A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer system having a multimedia bus and comprising a centralized I/O processor which performs intelligent data transfers
Assignee: GlobalFoundries Inc
•
Filing: 1996-05-17
•
Granted: 1998-05-19
•
Expires: 2016-05-17
Abstract
Abstract A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes a dedicated or centralized I/O processor coupled to one or more of the expansion bus and/or the multimedia bus which operates to direct or pull stream information through the system. The centralized I/O processor comprises a memory for storing data rate, data periodicity, data source, and data destination information for the multimedia devices. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.
Inventors
- 👤 Andy Lambrecht
- 👤 Scott Swanstrom
- 👤 Drew Dutton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:31
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/10; G06F13/12; G06F13/124; G06F13/368; G06F13/372; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022; G06F13/4027; H; H04; H04N; H04N21/00; H04N21/20; H04N21/23; H04N21/238
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
186 words
A computer system, comprising: a CPU; main memory coupled to the CPU which stores data accessible by the CPU; bridge logic coupled to the CPU and to the main memory, wherein the bridge logic includes a memory controller coupled to the main memory and also includes expansion bus interface logic; an expansion bus coupled to the bridge logic; one or more I/O devices coupled to the expansion bus, wherein the expansion bus provides electrical connections between the one or more I/O devices; a multimedia bus coupled to the bridge logic, wherein said multimedia bus includes a plurality of data lines for transmitting data; a plurality of multimedia devices coupled to said multimedia bus, wherein each of said multimedia devices perform operations on said multimedia bus, wherein each of said multimedia devices includes multimedia bus interface logic for accessing said multimedia bus and performing data transfers on said multimedia bus; and a centralized input/output processor coupled to said multimedia bus which controls operations on the multimedia bus, wherein the centralized input/output processor operates to direct data streams on the multimedia bus between the plurality of multimedia devices.
Claim 2
Dependent Claim
186 words
A computer system, comprising: a CPU; main memory coupled to the CPU which stores data accessible by the CPU; bridge logic coupled to the CPU and to the main memory, wherein the bridge logic includes a memory controller coupled to the main memory and also includes expansion bus interface logic; an expansion bus coupled to the bridge logic; one or more I/O devices coupled to the expansion bus, wherein the expansion bus provides electrical connections between the one or more I/O devices; a multimedia bus coupled to the bridge logic, wherein said multimedia bus includes a plurality of data lines for transmitting data; a plurality of multimedia devices coupled to said multimedia bus, wherein each of said multimedia devices perform operations on said multimedia bus, wherein each of said multimedia devices includes multimedia bus interface logic for accessing said multimedia bus and performing data transfers on said multimedia bus; and a centralized input/output processor coupled to said multimedia bus which controls operations on the multimedia bus, wherein the centralized input/output processor operates to direct data streams on the multimedia bus between the plurality of multimedia devices.
Claim 3
Dependent Claim
25 words
The computer system of claim 1, wherein said centralized input/output processor transmits one or more signals on said multimedia bus indicating a multimedia bus transfer.
Claim 4
Dependent Claim
25 words
The computer system of claim 2, wherein said centralized input/output processor performs addressing and control operations for transfers to be performed on said multimedia bus.
Claim 5
Dependent Claim
30 words
The computer system of claim 1, wherein said centralized input/output processor comprises a memory for storing data rate, data periodicity, data source, and data destination information for said multimedia devices.
Claim 6
Dependent Claim
61 words
The computer system of claim 4, wherein said centralized input/output processor includes data transfer control logic coupled to said memory which controls transfers on the multimedia bus, wherein said data transfer control logic uses said data rate, data periodicity, data source, and data destination information for said multimedia devices stored in said memory for controlling said transfers on the multimedia bus.
Claim 7
Dependent Claim
17 words
The computer system of claim 1, wherein said multimedia bus is the peripheral component interconnect (PCI) bus.
Claim 8
Dependent Claim
13 words
The computer system of claim 1, wherein said centralized input/output processor is programmable.
Claim 9
Dependent Claim
17 words
The computer system of claim 1, wherein said centralized input/output processor is comprised in said bridge logic.
Claim 10
Dependent Claim
201 words
A computer system, comprising: a CPU; main memory coupled to the CPU which stores data accessible by the CPU; bridge logic coupled to the CPU and to the main memory, wherein the bridge logic includes a memory controller coupled to the main memory and also includes expansion bus interface logic; an expansion bus coupled to the bridge logic; a multimedia bus coupled to the bridge logic, wherein said multimedia bus includes a plurality of data lines for transmitting data; a plurality of multimedia devices coupled to said expansion bus and said multimedia bus, wherein each of said multimedia devices perform operations on said expansion bus and said multimedia bus, wherein each of said multimedia devices includes expansion bus interface logic for accessing said expansion bus and performing data transfers on said expansion bus, and wherein each of said multimedia devices includes multimedia bus interface logic for accessing said multimedia bus and performing data transfers on said multimedia bus; and a centralized input/output processor coupled to said expansion bus and said multimedia bus which controls operations on the expansion bus and the multimedia bus, wherein the centralized input/output processor operates to direct data streams on the expansion bus and the multimedia bus.
Claim 11
Dependent Claim
201 words
A computer system, comprising: a CPU; main memory coupled to the CPU which stores data accessible by the CPU; bridge logic coupled to the CPU and to the main memory, wherein the bridge logic includes a memory controller coupled to the main memory and also includes expansion bus interface logic; an expansion bus coupled to the bridge logic; a multimedia bus coupled to the bridge logic, wherein said multimedia bus includes a plurality of data lines for transmitting data; a plurality of multimedia devices coupled to said expansion bus and said multimedia bus, wherein each of said multimedia devices perform operations on said expansion bus and said multimedia bus, wherein each of said multimedia devices includes expansion bus interface logic for accessing said expansion bus and performing data transfers on said expansion bus, and wherein each of said multimedia devices includes multimedia bus interface logic for accessing said multimedia bus and performing data transfers on said multimedia bus; and a centralized input/output processor coupled to said expansion bus and said multimedia bus which controls operations on the expansion bus and the multimedia bus, wherein the centralized input/output processor operates to direct data streams on the expansion bus and the multimedia bus.
Claim 12
Dependent Claim
29 words
The computer system of claim 9, wherein said centralized input/output processor performs addressing and control operations for transfers to be performed on said expansion bus and said multimedia bus.
Claim 13
Dependent Claim
30 words
The computer system of claim 9, wherein said centralized input/output processor comprises a memory for storing data rate, data periodicity, data source, and data destination information for said multimedia devices.
Claim 14
Dependent Claim
61 words
The computer system of claim 11, wherein said centralized input/output processor includes data transfer control logic coupled to said memory which controls transfers on the multimedia bus, wherein said data transfer control logic uses said data rate, data periodicity, data source, and data destination information for said multimedia devices stored in said memory for controlling said transfers on the multimedia bus.
Claim 15
Dependent Claim
17 words
The computer system of claim 9, wherein said multimedia bus is the peripheral component interconnect (PCI) bus.
Claim 16
Dependent Claim
17 words
The computer system of claim 9, wherein said expansion bus is the peripheral component interconnect (PCI) bus.
Claim 17
Dependent Claim
13 words
The computer system of claim 9, wherein said centralized input/output processor is programmable.
Claim 18
Dependent Claim
17 words
The computer system of claim 9, wherein said centralized input/output processor is comprised in said bridge logic.
References Cited (Backward Citations)
US4245344A
Cited
US5208745A
Cited
US4991169A
Cited
US5274784A
Cited
US5245322A
Cited
US5526017A
Cited
US5274763A
Cited
US5345566A
Cited
US5404463A
Cited
US5487167A
Cited
US5640543A
Cited
US5519839A
Cited
US5325423A
Cited
US5564001A
Cited
US5392407A
Cited
US5450551A
Cited
US5530902A
Cited
US5664218A
Cited
US5557757A
Cited
US5497373A
Cited
US5533205A
Cited
US5548730A
Cited
US5625779A
Cited
US5608651A
Cited
US5652614A
Cited
US5581552A
Cited
US5646676A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-18 | 2001-11-17 | 2002-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-18 | 2005-11-17 | 2006-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-18 | 2009-11-17 | 2010-05-19 | $7700.00 | Window Closed / Lapsed |