US5274784A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data transfer using bus address lines
Assignee: International Business Machines Corp
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Filing: 1991-11-13
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Granted: 1993-12-28
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Expires: 2011-11-13
Abstract
Abstract A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.
Inventors
- 👤 Ravi K. Arimilli
- 👤 Sudhir Dhawan
- 👤 James O. Nicholson
- 👤 David W. Siegel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 04:32
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
253 words
A system for transferring data in a digital computer, comprising: a bus having address lines, data lines, and control lines; a master subsystem connected to the bus; a slave subsystem connected to the bus; a first clock line in the bus for communicating a clock signal, wherein data is transferred between the master and the slave under control of the first clock signal when the system is in a first mode; a second, high speed, clock line in the bus for communicating a high speed clock signal, wherein data is transferred between the master and the slave under the control of the high speed clock signal when the system is in a second mode; a control line in the bus for communicating a transfer mode signal, wherein data is transferred between the master subsystem and the slave subsystem on the data lines when the transfer mode signal indicates that the system is operating in the first mode, and wherein data is transferred between the master subsystem and the slave subsystem on the data lines and on at least one of the address lines when the transfer mode signal indicates that the system is operating in the second mode; and control means connected to the slave subsystem for signalling to the master subsystem whether or not the slave subsystem is capable of transferring data in the second mode, wherein the second mode is used for data transfer only if both the master and slave subsystems are capable of transferring data in the second mode.
Claim 2
Independent Claim
253 words
A system for transferring data in a digital computer, comprising: a bus having address lines, data lines, and control lines; a master subsystem connected to the bus; a slave subsystem connected to the bus; a first clock line in the bus for communicating a clock signal, wherein data is transferred between the master and the slave under control of the first clock signal when the system is in a first mode; a second, high speed, clock line in the bus for communicating a high speed clock signal, wherein data is transferred between the master and the slave under the control of the high speed clock signal when the system is in a second mode; a control line in the bus for communicating a transfer mode signal, wherein data is transferred between the master subsystem and the slave subsystem on the data lines when the transfer mode signal indicates that the system is operating in the first mode, and wherein data is transferred between the master subsystem and the slave subsystem on the data lines and on at least one of the address lines when the transfer mode signal indicates that the system is operating in the second mode; and control means connected to the slave subsystem for signalling to the master subsystem whether or not the slave subsystem is capable of transferring data in the second mode, wherein the second mode is used for data transfer only if both the master and slave subsystems are capable of transferring data in the second mode.
Claim 3
Dependent Claim
28 words
The system of claim 1, wherein, prior to transferring data in the second mode, the master subsystem communicates an address on the address lines to the slave subsystem.
Claim 4
Dependent Claim
25 words
The system of claim 1, wherein the clock signal is an asynchronous clock signal, and the high speed clock signal is a synchronous clock signal.
Claim 5
Dependent Claim
18 words
The system of claim 1, wherein data is transferred during each cycle of the high speed clock signal.
Claim 6
Dependent Claim
24 words
The system of claim 1, wherein data is transferred on all of the address lines when the transfer mode signal indicates the second mode.
Claim 7
Independent Claim
185 words
A method for transferring data between a master subsystem and a slave subsystem over a computer system bus having address/data lines and data only lines, comprising the steps of: supplying a first clock signal from the master subsystem; initiating, by the master subsystem, a data transfer between the master subsystem and the slave subsystem; indicating, by the slave subsystem, whether the slave subsystem is capable of transferring data over the address/data lines using a high speed transfer; if the slave subsystem is capable of data transfer over the address/data lines, generating a high speed transfer clock signal in the master subsystem which is separate and distinct from a normal bus clock signal; if the slave subsystem is capable of data transfer over the address/data lines, transferring data between the master subsystem and the slave subsystem on the address/data lines and on the data only lines under the control of the high speed transfer clock; and if the slave subsystem is not capable of data transfer over the address/data lines, transferring data only over the data lines under the control of the normal bus clock signal.
Claim 8
Independent Claim
185 words
A method for transferring data between a master subsystem and a slave subsystem over a computer system bus having address/data lines and data only lines, comprising the steps of: supplying a first clock signal from the master subsystem; initiating, by the master subsystem, a data transfer between the master subsystem and the slave subsystem; indicating, by the slave subsystem, whether the slave subsystem is capable of transferring data over the address/data lines using a high speed transfer; if the slave subsystem is capable of data transfer over the address/data lines, generating a high speed transfer clock signal in the master subsystem which is separate and distinct from a normal bus clock signal; if the slave subsystem is capable of data transfer over the address/data lines, transferring data between the master subsystem and the slave subsystem on the address/data lines and on the data only lines under the control of the high speed transfer clock; and if the slave subsystem is not capable of data transfer over the address/data lines, transferring data only over the data lines under the control of the normal bus clock signal.
Claim 9
Dependent Claim
33 words
The method of claim 6, further comprising the step of: before the step of initiating a data transfer, communicating an address from the master subsystem to the slave subsystem on the address/data lines.
Claim 10
Dependent Claim
35 words
The method of claim 6, wherein the signal generated in the high speed transfer clock signal generating step has a speed limited by a maximum transfer rate of the master subsystem and the slave subsystem.
Claim 11
Dependent Claim
32 words
The method of claim 6, further comprising the step of: if the slave subsystem is not ready to transfer data, suspending data transfer until the slave subsystem is ready to transfer data.
Claim 12
Dependent Claim
28 words
The method of claim 6, wherein the normal bus clock signal is an asynchronous clock signal, and the high speed transfer clock signal is a synchronous clock signal.
Claim 13
Dependent Claim
61 words
The method of claim 10, wherein the data transfer initiating step is performed by transitioning the normal bus clock signal from a first state to a second state, and wherein the normal bus clock signal is held in the second state if data is transferred between the master subsystem and the slave subsystem under the control of the high speed clock.
Claim 14
Dependent Claim
24 words
The method of claim 6, wherein the transferring step comprises the step of transferring data during each cycle of the high speed clock signal.
Claim 15
Dependent Claim
66 words
The method of claim 6, wherein the high speed clock can be generated at at least two different speeds, and wherein the slave subsystem generates a signal indicating a maximum speed at which it can transfer data, and further wherein the master subsystem generates the high speed clock at a speed no greater than that which can be used by the slave subsystem for data transfer.
Claim 16
Dependent Claim
36 words
The method of claim 13, wherein the slave subsystem generates the maximum speed indicating signal at the same time as the signal indicating whether the slave subsystem is capable of transferring data over the address/data lines.
Claim 17
Independent Claim
167 words
A device for transferring data on a computer system bus having control lines, address/data lines and data only lines, comprising: means for communicating a starting address to the bus address/data lines; means for receiving a signal from the control lines indicating that a high speed transfer can be made over the bus; means for, in response to the receipt of the signal indicating that a high speed transfer can be made, generating a high speed bus clock signal on a separate signal line from a normal bus clock signal; means for, in response to the receipt of the signal indicating that a high speed transfer can be made, transferring data on the data only lines and on the address/data lines under the control of the high speed bus clock signal; and means for, in response to lack of receipt of the signal indicating that a high speed transfer can be made, transferring data on the data only lines under the control of the normal bus clock signal.
Claim 18
Independent Claim
167 words
A device for transferring data on a computer system bus having control lines, address/data lines and data only lines, comprising: means for communicating a starting address to the bus address/data lines; means for receiving a signal from the control lines indicating that a high speed transfer can be made over the bus; means for, in response to the receipt of the signal indicating that a high speed transfer can be made, generating a high speed bus clock signal on a separate signal line from a normal bus clock signal; means for, in response to the receipt of the signal indicating that a high speed transfer can be made, transferring data on the data only lines and on the address/data lines under the control of the high speed bus clock signal; and means for, in response to lack of receipt of the signal indicating that a high speed transfer can be made, transferring data on the data only lines under the control of the normal bus clock signal.
Claim 19
Dependent Claim
50 words
The device of claim 15, further comprising: means for limiting the speed of the high speed clock signal to a rate limited by a maximum transfer rate of another device connected to the bus; and means for suspending data transfer if the other device is not ready to transfer data.
Claim 20
Dependent Claim
28 words
The device of claim 15, wherein the normal bus clock signal is an asynchronous clock signal, and the high speed transfer clock signal is a synchronous clock signal.
Claim 21
Dependent Claim
29 words
The method of claim 17, further wherein a block of data is transferred between the master and slave subsystems while the normal system clock remains in the second state.
Claim 22
Dependent Claim
37 words
The method of claim 18, wherein the block of data has a last data item, and wherein such last data item is transferred by transitioning the normal bus clock from the second state to the first state.
Claim 23
Dependent Claim
91 words
The device of claim 17, further comprising: means for, in response to receipt of the signal indicating that a high speed transfer can be made over the bus, transitioning the normal bus clock signal from a first state to a second state; means for maintaining the normal bus clock signal in the second state while data is transferred under the control of the high speed clock; and means for transitioning the normal bus clock from the second state to the first state at the completion of the high speed data transfer.
Claim 24
Dependent Claim
36 words
The device of claim 20, wherein said means for transitioning the normal bus clock from the second state to the first state causes a last data item to be transferred under the control of such transition.
Claim 25
Dependent Claim
23 words
The device of claim 15, wherein the transferring means comprises means for transferring data during each cycle of the high speed clock signal.
Claim 26
Independent Claim
142 words
A device for transferring data on a computer system bus having control lines, address/data lines and data only lines, comprising: means for reading a starting address from the bus address lines; means for placing, in response to reading a starting address which selects the device, a signal onto the control lines indicating that the device can transfer data over the address/data lines; means for receiving a normal bus clock signal for control of data transfer; means for receiving a high speed clock signal, separate from the normal bus clock signal, for controlling a high speed data transfer over the system bus; means for transferring data on the data lines and on the address lines under the control of the high speed clock signal; and means for transferring data on the data only lines under the control of the normal bus clock signal.
Claim 27
Independent Claim
142 words
A device for transferring data on a computer system bus having control lines, address/data lines and data only lines, comprising: means for reading a starting address from the bus address lines; means for placing, in response to reading a starting address which selects the device, a signal onto the control lines indicating that the device can transfer data over the address/data lines; means for receiving a normal bus clock signal for control of data transfer; means for receiving a high speed clock signal, separate from the normal bus clock signal, for controlling a high speed data transfer over the system bus; means for transferring data on the data lines and on the address lines under the control of the high speed clock signal; and means for transferring data on the data only lines under the control of the normal bus clock signal.
Claim 28
Dependent Claim
43 words
The device of claim 23, further comprising: means for indicating a maximum data transfer rate for transfers made during high speed clock signal cycles; and means for indicating when the device is not ready to transfer data during high speed clock signal cycle.
Claim 29
Dependent Claim
28 words
The device of claim 23, wherein the normal bus clock signal is an asynchronous clock signal, and the high speed transfer clock signal is a synchronous clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-27 | 1997-06-28 | 1997-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-27 | 2001-06-28 | 2001-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-27 | 2005-06-28 | 2005-12-28 | $7700.00 | Window Closed / Lapsed |