US5533205A
Expired / Lapsed
US
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Method and system for efficient bus allocation in a multimedia computer system
Assignee: International Business Machines Corp
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Filing: 1994-03-30
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Granted: 1996-07-02
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Expires: 2014-03-30
Abstract
Abstract A method and system for efficient bus allocation in a multimedia computer system which includes a processor, a memory and multiple input/output devices which are coupled together via a bus which has a maximum data transfer rate. The transfer of audio, video, or other time sensitive data within the computer system to various presentation devices must be accomplished at certain predetermined rates in order to support selected applications. An arbitration level indicator which may be utilized to indicate a priority of bus access is associated with each presentation device which may contend for bus access. The bus access is then divided into a series of time frames which are subdivided into smaller time intervals. During selected time intervals the arbitration level indicators associated with a particular presentation devices are temporarily reordered to guarantee bus access at the required data rate.
Inventors
- 👤 John W. Blackledge, Jr.
- 👤 Bradly G. Frey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:37
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/3625
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
183 words
A method for efficient bus allocation in a computer system having a processor, a memory and a plurality of input/output devices coupled together via a bus having a maximum data transfer rate, said method comprising the computer implemented steps of: associating an arbitration level indicator with each of said plurality of input/output devices within said computer system; ordering said arbitration level indicators to indicate a priority of bus access for each associated input/output device; dividing access to said bus into a plurality of consecutive time intervals; and selectively and temporarily reordering said arbitration level indicators within particular ones of said plurality of consecutive time intervals by: determining a required data transfer rate for a particular input/output device; calculating a first percentage of said maximum data transfer rate of said bus required to meet said required data transfer rate; and designating an arbitration level indicator associated with said particular input/output device as a highest priority for bus access during a first percentage of said plurality of consecutive time intervals; wherein bus access for selected input/output devices may be guaranteed at predetermined fixed data rates.
Claim 2
Independent Claim
183 words
A method for efficient bus allocation in a computer system having a processor, a memory and a plurality of input/output devices coupled together via a bus having a maximum data transfer rate, said method comprising the computer implemented steps of: associating an arbitration level indicator with each of said plurality of input/output devices within said computer system; ordering said arbitration level indicators to indicate a priority of bus access for each associated input/output device; dividing access to said bus into a plurality of consecutive time intervals; and selectively and temporarily reordering said arbitration level indicators within particular ones of said plurality of consecutive time intervals by: determining a required data transfer rate for a particular input/output device; calculating a first percentage of said maximum data transfer rate of said bus required to meet said required data transfer rate; and designating an arbitration level indicator associated with said particular input/output device as a highest priority for bus access during a first percentage of said plurality of consecutive time intervals; wherein bus access for selected input/output devices may be guaranteed at predetermined fixed data rates.
Claim 3
Dependent Claim
61 words
The method for efficient bus allocation in a computer system according to claim 1, wherein said step of ordering said arbitration level indicator to indicate a priority of bus access for each associated input/output device comprises the step of numerically ordering said arbitration level indicators in a round-robin sequence to indicate a priority of bus access for each associated input/output device.
Claim 4
Dependent Claim
56 words
The method for efficient bus allocation in a computer system according to claim 1, wherein said step of dividing access to said bus into a plurality of consecutive time intervals comprises the steps of dividing access to said bus into a plurality of consecutive frames and dividing each frame into a plurality of consecutive time intervals.
Claim 5
Independent Claim
198 words
A system for efficient bus allocation in a computer system having a processor, a memory, and a plurality of input/output devices coupled together via a bus having a maximum data transfer rate, said method comprising the computer implemented steps of: means for associating an arbitration level indicator with each of said plurality of input/output devices within said computer system; means for ordering said arbitration level indicators to indicate a priority of bus access for each associated input/output device; means for dividing access to said bus into a plurality of consecutive time intervals; and means for selectively and temporarily reordering said arbitration level indicators within particular ones of said plurality of consecutive time intervals further comprising: means for determining a required data transfer rate for a particular input/output device; means for calculating a first percentage of said maximum data transfer rate of said bus required to meet said required data transfer rate; and means for designating an arbitration level indicator associated with said particular input/output device as a highest priority for bus access during a first percentage of said plurality of consecutive time intervals; wherein bus access for selected input/output devices may be guaranteed at predetermined fixed data rates.
Claim 6
Independent Claim
198 words
A system for efficient bus allocation in a computer system having a processor, a memory, and a plurality of input/output devices coupled together via a bus having a maximum data transfer rate, said method comprising the computer implemented steps of: means for associating an arbitration level indicator with each of said plurality of input/output devices within said computer system; means for ordering said arbitration level indicators to indicate a priority of bus access for each associated input/output device; means for dividing access to said bus into a plurality of consecutive time intervals; and means for selectively and temporarily reordering said arbitration level indicators within particular ones of said plurality of consecutive time intervals further comprising: means for determining a required data transfer rate for a particular input/output device; means for calculating a first percentage of said maximum data transfer rate of said bus required to meet said required data transfer rate; and means for designating an arbitration level indicator associated with said particular input/output device as a highest priority for bus access during a first percentage of said plurality of consecutive time intervals; wherein bus access for selected input/output devices may be guaranteed at predetermined fixed data rates.
Claim 7
Dependent Claim
60 words
A system for efficient bus allocation in a computer system according to claim 4, wherein said means for ordering said arbitration level indicator to indicate a priority of bus access for each associated input/output device comprises means for numerically ordering said arbitration level indicators in a round-robin sequence to indicate a priority of bus access for each associated input/output device.
Claim 8
Dependent Claim
55 words
A system for efficient bus allocation in a computer system according to claim 4, wherein said means for dividing access to said bus into a plurality of consecutive time intervals comprises means for dividing access to said bus into a plurality of consecutive frames and dividing each frame into a plurality of consecutive time intervals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-02 | 2000-01-01 | 2000-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-02 | 2004-01-01 | 2004-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-02 | 2008-01-01 | 2008-07-02 | $7700.00 | Window Closed / Lapsed |